Honored Contributor
Honored ContributorDear BadOmen,
Here is a feedback for your comments as I promised. According to your previous post I have also managed to access now the FPGA SDRAM / internal BRAM from the HPS portion (ARM side) at HWLib level. The key was to release the bridges from reset (init_bridge in hwlib.c). However, without DMA I have measured only 10 - 15 MB/s memory throughput (between ARM vs. FPGA memory) across HPS2FPGA bridge. Do you suggest any reference design, which integrates (FW/SW) and uses DMA? What is the role the h2f_reset signal in HPS (cylcone V handbook gives a few info)? Because as I experienced if I left this signal unconnected in qsys I can use both FPGA memory and HPS memory in a same FW design? The debounce circuit is also eliminated from golden HW/SW reference design. "Address Span Expander" bridge will be a good IP in the future, but I set all memory address spaces to a narrower size in order to be accessed by a 32-bit addresses of Nios II processor. Regards, ZS.V.
