Cyclone V SoC - Shared Memory Controller

I don't know of any designs that DMA data between the FPGA fabric and HPS using the DMA controller built into the HPS. Up on Rocketboards there should be a PCIe design that DMAs data using a soft DMA controll in the FPGA between the two FPGAs over PCIe. If you don't require a lot of throughput then you can use the HPS DMA controller. If you require a lot of throughput then a soft DMA in the FPGA fabric will make more sense since it will not cycle through multiple channels like the HPS DMA does.

The h2f_reset is provided so that you can trigger a reset into the FPGA fabric from the HPS. It is optional to use but typically if you reset the HPS you'll want to reset FPGA peripherals connected to the HPS as well.

The reason why I brought up the address span expander is because the Nios II masters only provide 32-bits of addressing. So if you connect Nios II to any of the HPS slave ports you won't have any address bits left over to connect Nios II to anything else. That's why the bridge between the Nios II master and HPS is necessary.