Cyclone V SoC - Shared Memory Controller

It seems Voroshazi and I are trying to do a very similar thing. I have also been working on moving data from the HPS to the FPGA SDRAM across the HPS2FPGA bridge. I too have been able to achieve this but have the same issue in that the throughput I am getting is in the order of 58MB/sec (by memcpy from HPS SDRAM to FPGA SDRAM). I'm not using a DMA either and wondered if you had been able to achieve better than this (I need at least 80MB/sec for my application)?