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Altera_Forum
Honored Contributor
Honored ContributorCyclone V SoC - Shared Memory Controller
Hi @all, I have a problem generating a Design with connection from FPGA to the HPS-Memorycontroller. I set up a QSYS-System with the connections and now try to get data from this Memory. ...
Altera_ForumHonored Contributor
Honored ContributorI don't know all the details but there is an issue with the way the preloader sets up the FPGA-to-SDRAM interfaces. So it's a software fix to resolve the issue. The issue only affects the read performance, so if you are seeing write performance issues then it is most likely something else going on.
