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Altera_Forum's avatar
Altera_Forum
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12 years ago

Cyclone V SoC - Shared Memory Controller

Hi @all, I have a problem generating a Design with connection from FPGA to the HPS-Memorycontroller. I set up a QSYS-System with the connections and now try to get data from this Memory. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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Also so that you don't spend time debugging a known issue, there is a known issue with the throughput between the FPGA and the HPS. This issue will be corrected in the next update.

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Can you elaborate more on this? I have some problems with the throughput. Are you referring to an update of Quartus, EDS, or the kernel?