Cyclone V custom board VCCIO puzzling behavior

Hello,

I have filed investigation request to engineering: 15018404392

This will take some time but engineering will take a look into this.

regards,

Farabi

Hello,

Let me check with internal team.

rgards,

Farabi

@Farabi

Any data on the leakage and what is root causes of such leakage?

Thank you

Hello,

1- You observed voltage increase at VCCIO power rails. How about the IO signals within the impacted VCCIO banks? Do you observed voltage increase as well?

2- Do this observation impacted any functional behavior of the device? like design failure, FPGA temperature increase etc?

regards,

Farabi

@Farabi

Thank you, finally there is FAE or staff can handle this ticket.

1) All
2a) for a development board form factor how could you expect all slot MUST used in any situations?
So of cause the situation happens on FMC slots is not used.
2b) As mentioned even setting this cannot see the effect is removed.

So this control on the EDA is so puzzling for what purpose?

3) as mentioned in this very beginning of this ticket, the adjustable DCDC buck converter is tested w/o the FPGA is applied and no voltage raised or out-off-range measurements are found. This is introduced by the FPGA Chip itself.

### add ups

** if configurated the unused pins to ground + output.
tested the pins do load to ground.

However, the power rails shows very low different 10-5mV different yet still raised a lot from 1.2 to 1.47.


Bests,

Brian

Hello,

I am taking over this case from previous owner.

How many devices you see the similar behavior?

This could possibly caused by VCCPD to VCCIO leakage current.

Do you have any undriven IOs with weak pullups?

Please make sure no VCCIO rails unconnected/unused especially FMC slots.

Can use pulldown resistors to stabilize the voltage.

regards,

Farabi

---

@BrianSune_Froum wrote:

I guess wait for vendor responses or guidance are a better choice.

---

Absolutely. After your latest post, I'm not even sure if we see irregular device behaviour at all or just operation beyond Cyclone V specifications.

As I'm working with Altera FPGA quite a long time, e.g. Cyclone V since 2014, I'm taking some specifications as granted, not considering that they might be misunderstood.

Hi,
I don't yet understand the relation to "open FMC slot". Or are you feeding VCCIO externally? Unusual, but no problem according to Cyclone V hot-socketing feature.

LVDS I/O standard for Cyclone V uses 2.5 V supply, How is LVDS signal related to 1.2V VCCIO.

You have previously reported VCCPD to VCCIO leakage, there should be no relation to I/O pin leakage. Or do you suspect that VCCIO 1.2 V is raised due to I/O voltage exceeding VCCIO rather than VCCPD? In this case, I/O pin leakage can matter.

Just for clarification:

- What's the configured I/O standard in the affected I/O bank(s)?
- Are I/O pins driven externally above VCCIO?

Regards
Frank

@FvM

Very simply, just like FMC slot ->Before any slot cards are inserted to the slot it is open.

Then an open slot will introduce a voltage as this ticket mentioned.

Why waste power on unnecessary resistor when it should not be the case.

Any development board could experience such issue before the slot is use.

So unless there is a good explanation VCCIO on 1.2V or 1.5V is risky as it introduce unexpected raise of VCCIO rail.

There are no deep investigation on driver IOs in purpose of the empty slot IO bank via dummy IO on HDL design.

So far there are no official response on this issue, and I can't see this is related to any external damage like ESD etc.

As for the leakage, this is also pure guess on diode or any pass-gate whatever leakage from the beginning, but after study more documents this is not the actual case.

So applying resistor to remove the raise on voltage rail is just covering the issue without really knowing what is the problem.

Such solution is just introduce lifespan hazard.

### More document study

The group of the FMC slot is 14 sets of LVDS.

Assuming 28 * 30uA = 840uA.

Assuming 1.2V at 840uA = 1k43 ~ =1k5

But this only applied to IO undriven as input case.

If my understand is correct. the default Quartus sets the undriven IO to input /w small pull-up.

However, even setting the project to output driven to ground only makes 10mV different.

So there must be s.t. missing from first place.

Hi,
I don't expect that this (apparently flawed, unclear transistor gate/source connection) principle schematic is helping to identify possible leakage paths between VCCPD and VCCIO node.

Not sure what you are trying to achieve, why has VCCIO 1.2 V supply high impedance in your design? Is there anything against applying a moderate pull-down resistor, e.g. 1k at VCCIO 1.2V rail?

Regards
Frank