KianHinT_altera
Frequent ContributorUser Profile
Frequent Contributor
User Widgets
Contributions
Re: Agilex5 - Bridge AXI F2H - read transactions
Hi ohfpga1 Apologies for the long delay in the response to your question. From the HPS reference manual document for Agilex 5, the recommendation is that width adaptation logic is required to handle 256-bit data packing and unpacking at the RDATA interface, not merely to translate ARADDR/ARSIZE/ARLEN parameters before presenting requests to the bridge. The F2H bridge returns data aligned to 256-bit boundaries (with potential null cycles for narrow requests) rather than true narrow beats, and requires AxSIZE to match the full 256-bit data bus width in the documentation also mentions about the rw/wr data must be equal to the data bus width Therefore, the width adapter logic must intercept the 64-bit master's request and translate the ARADDR, ARSIZE (forcing it to 0x5 for 256-bit), and ARLEN before presenting it to the F2H bridge on the request part. As width adapter forced the bridge to perform a standard full-width 256-bit, the bridge will in turn will return 256-bit aligned beats. The adapter must now act as a downsizer, capturing that 256-bit RDATA beat, unpacking it, and slicing it into the expected 64-bit beats with the correct valid/last signaling for the original master. In short the F2H bridge does not natively support standard AXI narrow reads thus width adaptation logic is needed to ensure the bridge is operating at 256bit (convert narrow AxSIZE request to 256bits) and to handle the unpacking of 256bit RDATA. Hope it addresses your question on the AXI F2H. Thanks Regards KianRe: How can I use Quartus Pro 25.1 sopc-create-header-files tool to generate a jtag master header file?
Hi DLiu5 Do you know or able to see where this directory located /sopc-create-header-files.38.tmp.swinfo or /tmp/sopc-create-header-files.38.tmp.swinfo failed? I suspect it might be trying to access linux folder in WSL which Windows cannot translate. Could you try again using the Nios Shell command prompt (i think this might resolve the directory issue where the script is trying to use linux native folder but windows cannot access) , but as you get command not found, it means that you dont have this path in your environment . Could you try add that inside the nios command shell (eg PATH=/altera_pro/25.1.1/quartus/sopc_builder/bin:$PATH <--make sure directory path is correct) and see whether still got the command not found error?Re: Agilex 5 Sulfur Partial Write Issue on F2H ACE‑Lite I/F (256‑bit) with AXI Master of 128‑bit
Hi Suresh, Sorry for the delay, was out of office. Previously I took a look on this , unfortunately there is no ready IP that can directly address this issue , documentation only mentioned about user needs to add a width adaptation interconnect logic but I didnt see any like examples from this. Initially thought maybe FIFO IP but on its own it does not have Write strobes (WSTRB) in AXI protocol for partial write so cannot be used directly. In other hand, i think you are already using the ACE5-Lite cache coherency translator or width adapter performing implicit RWR operations, converting partial 128-bit writes into full 256-bit cache line operations Have you considered instead of F2H, using F2SDRAM bridge instead to write the USB directly to the SDRAM bypassing the cache coherency unit and its width requirements? Otherwise, I think it is possible to use FIFO IP to handle the data packing and then using the ACE5 lite cache coherency translator IP to handle the transaction. You might need a custom state machine to manage the FIFO IP to wait for it to pack all the data 512bit? to avoid the RWR and trigger the translator when data 2x256bit is fulfilled. Thanks Regards KianRe: Agilex5 HPS2FPGA usage
Hi aJan, May I ask whether are you trying to use HPS or Nios for your design, as first phase it is HPS based, then 2nd phase you're using Nios Shell to run the quartus file generation? If you're using HPS, perhaps this guide will help (it is based on 24.1 since you're using 24.05) https://altera-fpga.github.io/rel-24.1/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/#build-sd-card-boot-binaries I suspect is because you're using the precompiled version of u-boot-spl.dtb.hex thus you're seeing some boot failures here, as any hardware mismatch between the precompiled configuration based on precompiled design vs the design that you have will result in error as it needs to matched correctly Could you try recompile the u-boot-spl-dtb.hex first following the guide on top, its compiled as part of yocto build and then proceed with the rest of the sequence per the guide. May I know your Quartus pro version as well? Usually we will advise to use the matching Quartus version with the release baseline. Thanks Kian
