KianHinT_altera
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Re: DE10-nano HPS boot from EPCS
Hi Hang The 2 pages from rocketboard already been obsolete if you're using a newer uboot/quartus version. You should refer to this page instead https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10 or this : https://altera-fpga.github.io/rel-25.3/embedded-designs/cyclone-v/sx/soc/boot-examples/ug-linux-boot-cve-soc/ Any changes using bsp-editor will not take effect anymore , and later version SOC EDS also become obsolete and no longer using. When building uboot, don't use the default make socfpga_cyclone5_defconfig as it is for the cyclone5 devkit, instead use the one for de0 nano (Socfpga_de10_nano_defconfig) . All the modification is to be done in defconfig or the devicetree file or .config Thanks Regards KianRe: F2SDRAM max burst length - Agilex5
Hi, Apologies for the delayed response as previously our embedded team did not monitor this forum category for embedded related question until we are notified by other teams . As for this issue, I saw there is a requirement that any transaction cannot cross a 4KB boundary in the AXI protocol document (https://developer.arm.com/documentation/ihi0022/latest/) . Is your transaction adheres to this requirement? Perhaps you can refer to this demo example https://github.com/altera-fpga/agilex5-demo-hps2fpga-interfaces/blob/main/documentation/09_menu_p_hw_f2sdram_bridge.md Thanks Regards KianRe: ERROR: Config PwrMgr handoff failed. error -1
KianHinT_altera Hi Milan, Could you try the steps listed by Rolando ? I suspect the new Quartus 25.3 have some differences in the HPS handoff data format, thus it will give error(in this case power manager/PwrMgr that requires some config data from FPGA) if there is a mismatch between Quartus generated handoff files and ATF/FSBL version. I was thinking probably you will need to regenerate the entire project in Quartus 25.3, then rebuild the ATF, uboot, zephyr that is based on QPDS25.3_REL_GSRD_PR with the 25.3 generated files, similar to what Rolando mentioned in his steps. Thanks Rolando for helping out in this case. Thanks Regards KianRe: Cyclone V H2F DMA is dead
Hi, Apologies for the delay in getting back on this case, just got back to office recently. I'm checking on the PL330 DMA driver but unfortunately I'm not able to see any removal notice in our internal database for Primecell PL330 DMA driver from uboot. I'm suspecting during the transition time from Altera - Intel where we switch databases thus probably the history is lost. There is also some questions asked in Rocketboard forums but unfortunately the site access is intermittent currently as they are transitioning from Rocketboards to Github https://forum.rocketboards.org/t/how-to-do-a-driver-for-hps-pl330-dma-controller/933 I've check our uboot (from 2020 onwards), didn't seems to have PL330 drivers either in uboot /arch/arm/include/asm/ nor in /drivers/dma folder although there is still some initialization in DTS (eg. socfpga.dtsi) also was searching around and I saw this adding ARM PL330 DMA driver in uboot (back in 2016) https://patchwork.ozlabs.org/project/uboot/patch/20161010155223.23751-2-dinguyen@kernel.org/ In some of the guide screenshot and KDB (for another issue) (https://www.intel.com/content/www/us/en/support/programmable/articles/000088369.html) , it seems the dma-pl330 is now loaded on kernel side (also there is the pl330 on kernel repo https://github.com/altera-fpga/linux-socfpga/blob/socfpga-6.12.19-lts/drivers/dma/pl330.c) It seems that you already found a solution to this case, if you dont mind, could you elaborate more on the solution? Thanks Regards KianRe: Arria10 HPS IP File missing
Hi, Sorry for the delay in response as I just got back to office, I tested on Quartus Pro Linux 25.1.1, 25.1 , 24.3, 23.3 and I can see the same behavior whereby IP file is listed as none for Arria 10. I checked our internal database and saw there was a case note that mentions Arria 10 altera_arria10_hps ships the HPS content as .qsys hardware project file instead of .ip file (similar to older devices eg. Cyclone V). For newer devices such as Stratix 10 , Agilex 7 onwards, the approach is to ship the HPS as a modular IP component with separate HPS IP releases for Platform Designer instantiation. Just FYI , there is Arria 10 GSRD user guide on generating the gsrd and other files https://altera-fpga.github.io/rel-25.1.1/embedded-designs/arria-10/sx/soc/gsrd/ug-gsrd-a10sx-soc/#compiling-hardware-design Note: for gsrd, the repo https://github.com/altera-opensource/gsrd-socfpga is no longer updated after 24.3, the new repo is this https://github.com/altera-fpga/arria10-ed-gsrd (will be updated in the document) Also discussed with our factory team to confirm that the warning(Warning message :- “Warning: File path could not be determined for component altera_arria10_hps in xxx.qsys. The component is ignored for generation.") could be safely ignored. Anyway, I noticed that by disabling the Parallel IP generation, it will remove the warning message on the File path could not be determined. Thanks. Regards Kian
