BrianSune_Froum
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Re: Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP - Hard Reset to Soft Reset
Ok the solution to resolve SRC under Hard PCIe RP: The example from rocketchip and MitySOM gate the mgmt reset by nreset_status. Due to pin_perst is not used -> 1'b1 The nreset_status will not release unless mgmt is reset with npor while gating mgmt reset by nreset_status will dead lock and never exit the reset.17Views0likes0CommentsRe: Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset
Ok the solution to resolve SRC under Hard PCIe RP: The example from rocketchip and MitySOM gate the mgmt reset by nreset_status. Due to pin_perst is not used -> 1'b1 The nreset_status will not release unless mgmt is reset with npor while gating mgmt reset by nreset_status will dead lock and never exit the reset.29Views0likes0CommentsRe: Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset
RongY_altera I am amazed how can you run lspci when root port not even exist? Maybe another Altera staff can help this ticket? Feels like you are not well understand the entire PCIe system. And stop quoting useless stackexchange this is completely not related this ticket nor what it is asking. Thanks20Views0likes1CommentRe: Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset
RongY_altera Can you read carefully previous posts? BrianSune_Froum wrote: The issue is changing from HRC to SRC introduce stuck or hang on Linux driver load. This is referring to the PCIe itself not slot card nor end-point devices. You are not even able to type any thing as it stuck or hang once the pcie-altera.ko insert. Thanks18Views0likes3CommentsRe: Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset
RongY_altera Can you read previous posts? I am not focusing on npor problem The issue is changing from HRC to SRC introduce stuck or hang on Linux driver load. Where the HRC case did not have such issue. Thanks21Views0likes5CommentsRe: Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset
Hi Altera, More info: Based on the STLA, it looks like the reconfiguration calibration never turn low after reset. While HRC can work without any issue. The SRC simply feed 1'b1 to the pin_perst and please do help or provide instruction to fix this trouble. Thanks, Brian40Views0likes8CommentsAvalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset
Dear Intel, Based on the forum info and datasheet it is allow to use soft reset rather than hard reset. In order to do so, changing <parameter name="force_src" value="0" /> to <parameter name="force_src" value="1" /> Should basically turn the HRC to SRC. However during actual system test SRC stuck on driver loaded while HRC does not. According to the above background informations: 1: do SRC allowed in GEN1 PCIe 2: How to properly driven the reset signal under verilog possible example could be good. Thanks, BrianSolved66Views0likes9CommentsAvalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP - Hard Reset to Soft Reset
Dear Intel, Really having a hard time on switch to soft reset. According to datasheet and forum discussion. Hard reset on the hard PCIe require a specified pin or pins to work. In order to fully make use all LVDS pairs inside the same bank of the hard PCIe reset pin, it is a must to use soft reset. Under testing the hard reset pin can function properly on root port design. Once we changed to soft reset under xxxx.qsys: <parameter name="force_src" value="1" /> After loading the driver on linux via insmod xxx.ko It immediately stuck. The reset is based on https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/PCIe_Hard_IP assign pcie_npor_pin_perst = pcie_reset ? ~pcie_reset : 1'bz; assign pcie_npor_npor = hps_fpga_reset_n & pcie_npor_pin_perst .pcie_cv_hip_avmm_0_npor_npor (pcie_npor_npor), .pcie_cv_hip_avmm_0_npor_pin_perst (pcie_npor_pin_perst), "pcie_reset" signal is generated by PIO IP Thanks, BrianSolvedRe: Cyclone V HPS FPGA2SDRAM Clock Queries
tehjingy_Altera For latest test I had committed. I am streaming camera data and forwarding to monitor ouput. It can be free run completely w/o distro intervein. Based on the above background when the input stream data is 90M and h2fsdram uses 100M on issue. However once I increase the clock from 100 ->148 then the distro terminal stall and serial port no longer responds. But the monitor forward shows the internal operation is working properly which means camera stream is forwarding to monitor w/o issue each frame is shown properly. The major issue here is why distro now got stall and stuck and completely dead? Brian20Views0likes0CommentsRe: Cyclone V HPS FPGA2SDRAM Clock Queries
tehjingy_Altera L4 and L3 on dts should be turned on by default? CMA is turned on and sweap disk is set. The only possible cause that could trigger kernel stall or distro crash is the sdram controller are stuck by other bridge. But this is still questionable that if a burst write is issued and the bus holds for new data arrive. How long that holds are allowed on AXI3 and could his hold even trigger any controller crash from first place? Those are my questions. Brian23Views0likes0Comments