BrianSune_Froum
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Re: Cyclone 5 SoC FPGA Bank Supply Prerequisite
AqidAyman_Altera Then this is violating the HMC standard. When slot cards are not used the VCCIO could be floated and no supplied. I cannot see the correlation between VCCIO and JTAG program fail. VCCIO had nothing to do with JTAG scan unless JTAG is located in VCCIO 5A/5B. VCCPGM or VCCIO BANK 3 is only the possible IO bank that can affected. So which handbook or document have detail info on such. Thanks, Brian5Views0likes0CommentsCyclone 5 SoC FPGA Bank Supply Prerequisite
Dear Altera Support Team, I am not sure this is correct and did not found much info on Handbook. Device 5CSXF6C6U23 CASE 1: BANK 5A 5B only supplied VCCPD to 2.5V and VCCIO is floated. JTAG scan chain shows both HPS and FPGA devices. JTAG program shows failed with wrong device address. CASE 2: BANK 5A 5B supplied 2.5V or 1.8V VCCIO. JTAG scan chain shows both HPS and FPGA devices. JTAG program shows successful result. Based on the above situation: do BANK 5 must supplied VCCIO in order FPGA to work? I don't understand, other brand FPGA do not have such requirement while VCCPD must be powered which is understandable. Please confirm this for best and safe device HW configuration. Thanks, BrianRe: Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP - Hard Reset to Soft Reset
Ok the solution to resolve SRC under Hard PCIe RP: The example from rocketchip and MitySOM gate the mgmt reset by nreset_status. Due to pin_perst is not used -> 1'b1 The nreset_status will not release unless mgmt is reset with npor while gating mgmt reset by nreset_status will dead lock and never exit the reset.30Views0likes0CommentsRe: Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset
Ok the solution to resolve SRC under Hard PCIe RP: The example from rocketchip and MitySOM gate the mgmt reset by nreset_status. Due to pin_perst is not used -> 1'b1 The nreset_status will not release unless mgmt is reset with npor while gating mgmt reset by nreset_status will dead lock and never exit the reset.37Views0likes0CommentsRe: Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset
RongY_altera I am amazed how can you run lspci when root port not even exist? Maybe another Altera staff can help this ticket? Feels like you are not well understand the entire PCIe system. And stop quoting useless stackexchange this is completely not related this ticket nor what it is asking. Thanks25Views0likes1CommentRe: Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset
RongY_altera Can you read carefully previous posts? BrianSune_Froum wrote: The issue is changing from HRC to SRC introduce stuck or hang on Linux driver load. This is referring to the PCIe itself not slot card nor end-point devices. You are not even able to type any thing as it stuck or hang once the pcie-altera.ko insert. Thanks24Views0likes3CommentsRe: Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset
RongY_altera Can you read previous posts? I am not focusing on npor problem The issue is changing from HRC to SRC introduce stuck or hang on Linux driver load. Where the HRC case did not have such issue. Thanks35Views0likes5CommentsRe: Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset
Hi Altera, More info: Based on the STLA, it looks like the reconfiguration calibration never turn low after reset. While HRC can work without any issue. The SRC simply feed 1'b1 to the pin_perst and please do help or provide instruction to fix this trouble. Thanks, Brian42Views0likes8CommentsAvalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset
Dear Intel, Based on the forum info and datasheet it is allow to use soft reset rather than hard reset. In order to do so, changing <parameter name="force_src" value="0" /> to <parameter name="force_src" value="1" /> Should basically turn the HRC to SRC. However during actual system test SRC stuck on driver loaded while HRC does not. According to the above background informations: 1: do SRC allowed in GEN1 PCIe 2: How to properly driven the reset signal under verilog possible example could be good. Thanks, BrianSolved90Views0likes9CommentsAvalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP - Hard Reset to Soft Reset
Dear Intel, Really having a hard time on switch to soft reset. According to datasheet and forum discussion. Hard reset on the hard PCIe require a specified pin or pins to work. In order to fully make use all LVDS pairs inside the same bank of the hard PCIe reset pin, it is a must to use soft reset. Under testing the hard reset pin can function properly on root port design. Once we changed to soft reset under xxxx.qsys: <parameter name="force_src" value="1" /> After loading the driver on linux via insmod xxx.ko It immediately stuck. The reset is based on https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/PCIe_Hard_IP assign pcie_npor_pin_perst = pcie_reset ? ~pcie_reset : 1'bz; assign pcie_npor_npor = hps_fpga_reset_n & pcie_npor_pin_perst .pcie_cv_hip_avmm_0_npor_npor (pcie_npor_npor), .pcie_cv_hip_avmm_0_npor_pin_perst (pcie_npor_pin_perst), "pcie_reset" signal is generated by PIO IP Thanks, BrianSolved