BrianSune_Froum
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Re: Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations
CheepinC_altera I want your test project to cross check the setup of your full-duplex is align with what we are expecting. That you placed 3 custom duplex and 1 TX with 2 channel PCIe, I think there is sometime not aligned. Thanks, Brian CheepinC_altera There is still an issue on CH4 where you claim you had successfully fitter TX on that channel. However this is unable to achieve from beginning to current state: Where either CH2 CH3 CH5 also good to place whatever custom design. So how you actually constraints or what settings are done to make this possible?Re: Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations
CheepinC_altera You are just repeating what I had done. This is making no sense, what I am asking is that can or could it possible to use PCIex4 with 2 custom phy in any form of configuration. CheepinC_altera BTW I had successfully fitter top with individual recfg controller. On PCIe X2 case so please try it yourself. This had violate what you had concluded.Re: Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations
CheepinC_altera I can only share the IP from altera all other logic and block will be cropped if this is ok for you I will cont'd to do so. Q: I think the major issue here is reconfiguration block 1 -> top 1->bottom only 1 on each. so if the reconfiguration block already hold by PCIe there is not way additional transceiver can run on different speed unless it is same as PCIe spec. So before we spend time on this maybe have a look on Q: CheepinC_altera I am not sure you are altera FAE staff or just regulator forum contributor? However, I think if you have idea have to do it you should able to use this to validate what we are discussing. Fair enough for my side to provide this and I cannot see why there are no easy test on your side to validate this as well. Thanks, BrianRe: Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations
CheepinC_altera Again I really want official answer on the actual placement validation. For what I do a quick placement test it never work unless [CH3 CH5] only CheepinC_altera The fitter report reconfiguration placement issue CheepinC_altera It is very hard to trace the fitter issue from just a simple error message. b.c. it never explain nor mention the actual resource tried to route is not feasible by what causes. However based on our long discussions: Question or original placement of PCIe IP block why require CH4 but not CH1 in the first place? Without understanding this in the first place we can only guess it is not able to share CMU PLL with TRX otherwise resources speaking why additional place CH4 not CH1 in the first place? Next, channel placements are just a small part of the transceiver design w/o the reconfiguration it cannot function as well. So LSS: can it be as simple as a table that what is the possible combination of transceiver placements? Thanks, BrianRe: Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations
CheepinC_altera LSS: The goal here is to find the possible usage or maximum usage on these GXB. PCIe is a must the reduction to x2 is also good enough as x4 itself do not really gain much BW via HPS. So if possible x4 on remain GXB is what we expected. bottom [0|1] <- PCIe x2 bottom [2] + top[3|5] [4] ? 4 channel via fPLL x2 ??Re: Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations
CheepinC_altera I will get back to you after testing CheepinC_altera Quick fitting test shows: PCIe X2 GEN 1 (max speed on this device) + Custom x2 protocol < (3.125Gbps) Can be placed on [Ch0+Ch1(Ch4)] + [Ch3,Ch5] Total GXB usage 4 So simply speaking The maximum possible GXB can only be 5 and never 6? I still don't get it: Why channel 4 cannot be used as TRX when CMU PLL is placed. Aren't the internal function block supposed to be stand alone? Meantime, from the above test result: For PCIe x4 the expected Ch5 can be placed by fPLL. So the best cases are Total of 5 TxR channels? CheepinC_altera Additional placement view info: You can see it is completely empty for use but why CMU use case make if unusable? Meantime the GXB TX use case shows a very distinct placement. It is very ＂Counterthinking" on this fitter idea!!! Thanks, BrianRe: Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations
CheepinC_altera A bit hard to understand on: "However, whether this approach is supported and can be successfully placed depends on the specific design constraints and routing availability. In this scenario, it is likely that two fPLLs would be required (1 for bottom 3 channels and another for top 3 channels), but this cannot be confirmed upfront." What do you mean constraint so you do mean there is constraint that can force or make it routable? And what do you mean routing availability? Two fPLLs is due to what bases and how about the x1 xN configuration? The device had been years over decade aren't these configuration possibilities are very well documented? Thanks, BrianRe: Cyclone V SoC 5CSXC6 Series GXB Utilization and Limitations
Dear Intel/Altera, I want a neat answer: For one side GXB confirmations: 3+3 bottom+up When PCIe is used: What are the possible combination on Hard Core PCIe + custom GXB design. Either CMU PLL or fPLL design on xN or x1. I am a bit lost on the handbook. TBH, reading it feels like it can configure as 6 but turns on the fitter does not. So this is very puzzling. Thanks, Brian
