BrianSune_Froum
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Re: Cyclone V HPS FPGA2SDRAM Clock Queries
tehjingy_Altera For latest test I had committed. I am streaming camera data and forwarding to monitor ouput. It can be free run completely w/o distro intervein. Based on the above background when the input stream data is 90M and h2fsdram uses 100M on issue. However once I increase the clock from 100 ->148 then the distro terminal stall and serial port no longer responds. But the monitor forward shows the internal operation is working properly which means camera stream is forwarding to monitor w/o issue each frame is shown properly. The major issue here is why distro now got stall and stuck and completely dead? Brian7Views0likes0CommentsRe: Cyclone V HPS FPGA2SDRAM Clock Queries
tehjingy_Altera L4 and L3 on dts should be turned on by default? CMA is turned on and sweap disk is set. The only possible cause that could trigger kernel stall or distro crash is the sdram controller are stuck by other bridge. But this is still questionable that if a burst write is issued and the bus holds for new data arrive. How long that holds are allowed on AXI3 and could his hold even trigger any controller crash from first place? Those are my questions. Brian8Views0likes0CommentsRe: SDRAM calibration failed.
qwitza I encounter the same issue. All previous mainstream U-Boot and Altera U-Boot working properly. But just pull to newer U-Boot that tedious message print. However keep reset manually via master reset button can trigger a normal boot. So it must be s.t. messed up on patches. No it is not about the device issue, it is U-Boot software issue. Brian30Views0likes0CommentsRe: Cyclone V HPS FPGA2SDRAM Clock Queries
tehjingy_Altera Please use "@" to reply the system did not email notification. For this explanation, it is not given out the possible cause of stall on distro. In order for system stall the sdram data must be runed or corrupted. However with proper address R/W there is no way to trigger such action. So why during boot or when system is stable once the high throughput write could introduce this issue? Could you provide a check method for L3/L4 is enable? I think there maybe cache that is not turned on?15Views0likes0CommentsRe: Cyclone V HPS FPGA2SDRAM Clock Queries
tehjingy_Altera Ok, more info for this situation. KEY 1: If data is kept reading on f2h_sdram0 148M no issue is found. Once the f2h_sdram1 is enable via some control and start stream at 144M the system stall on distro. However, the data r/w on bus f2h_sdram0 andf2h_sdram1 are functioning properly. The only issue is the system aka the CPU is stall and terminal no longer response. The most interesting thing is that the background FPGA fabric are all functioning like free-run w/o any stall or data stuck. Well the same design with only slowing down the f2h_sdram1 from 144M to 100M fixed all the issue. f2h_sdram0 <- mostly read f2h_sdram1 <- mostly write So when 144M is used onf2h_sdram1 and once the CPU is stall. All data read / write are still working. read streams write streams are all functioning via some interface to verify. Brian33Views0likes7CommentsCyclone V HPS FPGA2SDRAM Clock Queries
Dear Intel and all, Having some very puzzling behavior on HPS SDRAM and FPGA fabric bridge. If a fast clock i.e. 148MHz is running on 128bit AXI3 aka f2h_sdram0 mostly read action. And another AXI3 is using the remain 128bit bus with 144MHz aka f2h_sdram1 mostly on write. As such the system will stuck on distro aka Linux. With all these background could engineer or internal stuffs help. What is the restriction or constraints to use these bus under safe and stable speed? Forgot to provide stable situation: If the write dominated bus is reduced to 100MHz then the system is stable and no stall is found. So this makes a very strong feeling that the write cache is having issue? maybe CMA insufficient? BrianRe: SD Card Boot
@RolandoS_Altera I had mentioned again, the upstream 01 04 u-boot can work but requires modification as default cyclone V config not longer plug and play as old ones. Again, you just repeated what I had said. Why U-Boot could be device dependent from first place. I guess there are no point to loop in such. I had made my points and either stuff take action or not is a choice from Altera.43Views0likes0CommentsRe: SD Card Boot
@SueC_Altera Quote: "Hi, I have an Agilex 5 Modular Development Board which I can boot with the supplied SD Card. I have tried to update to the latest image at Index of /2025.04/gsrd/agilex5_mk_a5e065bb32aes1_gsrd/, However, after programming an SD Card with this image, as far as I can tell, my board doesn't boot. I get no output from the serial port so I don't have any way of debugging. Please can you help with any advice how to proceed to diagnose what is going wrong? Many thanks Malcolm" According to this quote aka the first comment in this ticket. Could you read "no output from the serial port" <----- Such behavior is 100% aligned with 2025.01 2025.04 U-Boot Altera github repository on C5 devices. I don't see why all stuff comments are so confused on this same issue. And I had already explained the issue and the possible solutions accordingly, which might not fix as inherent issue of this early year that Das U-Boot upstream had changed the SPL settings entirely. I no expert on Uboot but undergo minor study on such. So if there are system Engineer from Altera should know very well.97Views0likes2CommentsRe: SD Card Boot
@SueC_Altera You are also misread the topic. What this original ticket is about SD Card U-Boot booting on Ag5. I don't understand why you guys will consider U-Boot is device dependent. As for what the title mentioned is no device orientated. As such I cannot understand at what points / posts / questions that are not U-Boot related question from first place.136Views0likes0Comments