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BrianSune_Froum's avatar
BrianSune_Froum
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2 months ago
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Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP Soft Reset and Hard Reset

Dear Intel, Based on the forum info and datasheet it is allow to use soft reset rather than hard reset. In order to do so, changing <parameter name="force_src" value="0" /> to <parameter name="f...
Pcie
  • BrianSune_Froum's avatar
    BrianSune_Froum
    1 month ago

    Ok the solution to resolve SRC under Hard PCIe RP:

    The example from rocketchip and MitySOM gate the mgmt reset by nreset_status.

    Due to pin_perst is not used -> 1'b1

    The nreset_status will not release unless mgmt is reset with npor while gating mgmt reset by

    nreset_status will dead lock and never exit the reset.

BrianSune_Froum's avatar
BrianSune_Froum
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1 month ago

RongY_altera​ 

I am amazed how can you run lspci when root port not even exist?

Maybe another Altera staff can help this ticket?

Feels like you are not well understand the entire PCIe system.

And stop quoting useless stackexchange this is completely not related this ticket nor what it is asking.

Thanks

  • RongY_altera's avatar
    RongY_altera
    Icon for Contributor rankContributor
    1 month ago

    I was not aware of this is a RP use case so my previous suggestions were not aligned to your needs.

     

    I noticed you have another similar topic in the forum with better statement. 

    https://community.altera.com/discussions/fpga-device/avalon-mm-cyclone-v-hard-ip-for-pci-express-intel-fpga-ip---hard-reset-to-soft-r/350590

     

    To prevent duplicate threads on the same issue, this topic will be closed. Thanks for your understanding.

     

    Regards,

    Rong