tehjingy_Altera
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Re: ARM DS5 debugger Access/Detection of CM55 on Agilex5 fpga device
Hi Suresh430 Case 2 would be the route you should look at. The Virtual JTAG IP does not have the protocol to connect to the CoreSight DAP. If you would like to connect it through the Virtual JTAG IP you would need to create the "JTAG to Coresight bridge IP" which would connect the Virtual JTAG IP to the Coresight DAP, which is currently unavailable in the Catalog IP.0Views0likes0CommentsRe: Agilex 5E: How to access FPGA-side EMIF DDR4 from HPS through HPS2FPGA?
Hi amsssss123 Yes the hps2fpga_clk and the hps2fpga_rst are referencing to the hps2fpga_axi_clock and hps2fpga_axi_reset mentioned. For the EMIF Clock in the first screenshot it is shows the Access Mode of the EMIF is in Sync Mode with a clock out present, it should be connected to the hps2fpg_clk. If it is in Async Access Mode both hps2fpg_clk and s0_axi4_clk should be connected to the same clock source.13Views0likes1CommentRe: ARM DS5 debugger Access/Detection of CM55 on Agilex5 fpga device
Hi Suresh430 There is no officially recommended debug probe. As long as the probe supports the CoreSight DAP then it should work. As for the licensing, I am not be the best person to advice on this but if you could contact your DFAE that help with the purchase, they would advise you on this.4Views0likes2CommentsRe: ARM DS5 debugger Access/Detection of CM55 on Agilex5 fpga device
Hi Suresh430 I dont think it is possible for a Custom Design with Cortex-M55 to appear in the native Jtag chain. The connection of the HPS DAP is done internally. For your case, a suggestion is to follow the route of an additional Jtag connection for the DAP sole purpose of debugging eh Cortex-M55.8Views0likes4CommentsRe: Arria 10 QSPI controller hangs after U-Boot shell while SPL boots successfully
Hi LironAvrhmov Is it possible if you could share your hps.xml in the handoff folder? Try comparing the non-working handoff file with the working. Check if the pinmux generate matches with the peripherals selected under the HPS IP.6Views0likes0CommentsRe: F2SDRAM fails to synthesize with custom logic
Hi HPark14 This error behavior is expected because the F2SDRAM interface must be properly connected, as mentioned by my colleague, kbrunham_altera . For reference, you can refer to the public design example below. It connects the unused F2SDRAM port to a no_periph subsystem, which effectively terminates the interface and satisfies this design requirement: https://github.com/altera-fpga/agilex5-demo-hps2fpga-interfaces/tree/main/brd_altera_a5e065_premium_es/hw_base I hope this helps.25Views1like3Comments