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tehjingy_Altera
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Re: RSU: Corrupted decision firmware after loading initial RSU image jic (Stratix 10)
Hi plancheres The likely issue is that factory.rbf and the application RBFs are signed, but factory_boot.rbf was generated as an unsigned RBF: quartus_pfg -c factory_image.sof factory_boot_unsigned.rbf -o rsu_boot=ON Please sign the generated BOOT_INFO RBF using the same signing chain and private key used for the factory image: quartus_sign --family=stratix10 --operation=sign \ --qky=<signing_chain.qky> \ --pem=<signing_private_key.pem> \ factory_boot_unsigned.rbf factory_boot_signed.rbf Update Bitstream 1 in the PFG to use the signed file: <bitstream id="Bitstream_1"> <path>factory_boot_signed.rbf</path> </bitstream>118Views0likes1CommentRe: Intermittent DE10-Standard error starting GDB server with quartus_hps
Hi What is the Jtag clock frequency that you are using? Could you try reducing the JtagClock frequency ? Try 16Mhz or 6Mhz. You could use the command below to change the frequency: jtagconfig --setparam <cable_index> JtagClock <frequency>16Views0likes1CommentRe: ARM DS5 debugger Access/Detection of CM55 on Agilex5 fpga device
Hi Suresh430 Case 2 would be the route you should look at. The Virtual JTAG IP does not have the protocol to connect to the CoreSight DAP. If you would like to connect it through the Virtual JTAG IP you would need to create the "JTAG to Coresight bridge IP" which would connect the Virtual JTAG IP to the Coresight DAP, which is currently unavailable in the Catalog IP.4Views0likes0CommentsRe: Agilex 5E: How to access FPGA-side EMIF DDR4 from HPS through HPS2FPGA?
Hi amsssss123 Yes the hps2fpga_clk and the hps2fpga_rst are referencing to the hps2fpga_axi_clock and hps2fpga_axi_reset mentioned. For the EMIF Clock in the first screenshot it is shows the Access Mode of the EMIF is in Sync Mode with a clock out present, it should be connected to the hps2fpg_clk. If it is in Async Access Mode both hps2fpg_clk and s0_axi4_clk should be connected to the same clock source.57Views0likes3Comments