tehjingy_Altera
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Re: Cyclone V CAN triple sampling
Hi prmartinuk The Cyclone V do not have the CAN Triple sampling. There is no option to change the sampling rate of the CAN in the HPS. You could find other register setting for the CAN in the Cyclone V HPS Register Map in the link below: https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html#sfo1410070054239.html#sfo1410070054239 Regards tehjingy4Views1like0CommentsRe: NIOS V: Systick based timeouts not available when using internal timer
Hi FabianL That issue that you are facing is valid and we are currently looking into it. As a workaround currently could you try modify the generated alt_sys_init function to have the INTEL_NIOSV_M_INIT before the rest as shown below: void alt_sys_init( void ) { INTEL_NIOSV_M_INIT ( NIOS_SUBSYSTEM_INTEL_NIOSV_M_0, nios_subsystem_intel_niosv_m_0); ALTERA_AVALON_TIMER_INIT ( NIOS_SUBSYSTEM_TIMER_0, nios_subsystem_timer_0); ALTERA_AVALON_JTAG_UART_INIT ( NIOS_SUBSYSTEM_JTAG_UART_0, nios_subsystem_jtag_uart_0); ALTERA_AVALON_SPI_INIT ( NSC3_SUBSYSTEM_0_ADC_SPI, nsc3_subsystem_0_adc_spi); ALTERA_AVALON_SYSID_QSYS_INIT ( NIOS_SUBSYSTEM_SYSID_NIOS, nios_subsystem_sysid_nios); ALTERA_AVALON_UART_INIT ( NIOS_SUBSYSTEM_UART_IP, nios_subsystem_uart_ip); } For further details refer to the KDB : https://community.altera.com/kb/knowledge-base/why-does-the-nios%C2%AE-v-processor-that-applies-fast-jtag-uart-driver-stop-stuck-in-/34948112Views0likes0CommentsRe: Issue with configuring EPCQ64A & Cyclone10LP using NiosV as processor.
Hi Arpitmishra Could you describe what error you are facing when trying to access the flash? Are you able to read any values or write data to flash in NiosV? I believe you are using the GSFI IP to access the flash am I right?8Views0likes0CommentsRe: Agilex5 Eagle ES, NIOS-V + TSE IP
Hi ove You could take a look at the ED NiosV +TSE IP in the link below: https://altera-fpga.github.io/rel-25.3/embedded-designs/agilex-5/e-series/premium/niosv/niosv_g/webserver_ping/ug-webserver-ping-agx5e-premium/#nios-vg-ping-application-litert-design-architecture17Views0likes0CommentsRe: Recommended Quartus Prime Standard Edition for Nios V Development on MAX 10 FPGA (10M25DAF4817G)
Hi zjyoof For the error seen that could not halt. Try reducing the jtag frequency with the command and try again: jtagconfig --setparam <cable number> JtagClock <frequency><unit prefix>11Views0likes0CommentsRe: Issue with configuring EPCQ64A & Cyclone10LP using NiosV as processor.
Hi Arpitmishra For the NiosV are you running the NiosV application XIP in the EPCQ64A? What is the behavior when you try to access the memory inside the flash? If you are running the NiosV XIP on the flash, you should be able to read from the flash but it is not possible to write to the flash. Regards Jingyang, Teh22Views0likes2CommentsRe: Quartus Error When No Read Path Exists on F2H Bridge
Dear Customer, Since a solution is provided and no further clarification is needed on this thread, it will be transitioned to community support for further help on doubts in this thread. Please login to the Altera Community Forum and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Thank you for the questions and as always pleasure having you here. Best Wishes Altera Tech Support28Views0likes0Comments