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Re: Issue with configuring EPCQ64A & Cyclone10LP using NiosV as processor.
Hi Arpitmishra For the NiosV are you running the NiosV application XIP in the EPCQ64A? What is the behavior when you try to access the memory inside the flash? If you are running the NiosV XIP on the flash, you should be able to read from the flash but it is not possible to write to the flash. Regards Jingyang, Teh10Views0likes1CommentRe: Quartus Error When No Read Path Exists on F2H Bridge
Dear Customer, Since a solution is provided and no further clarification is needed on this thread, it will be transitioned to community support for further help on doubts in this thread. Please login to the Altera Community Forum and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Thank you for the questions and as always pleasure having you here. Best Wishes Altera Tech Support1View0likes0CommentsRe: University Program IP for NiosV
Hi tjmsoe Sorry for the misinformation. The team just got back to me that there will not be a community page specific to the University Program. You would need to post to the respective community page base on the issue you face. Regarding the University Program IP blocks, what exactly are the IPs that you would like it to be migrated to the NiosV Platform?6Views0likes0CommentsRe: Recommended Quartus Prime Standard Edition for Nios V Development on MAX 10 FPGA (10M25DAF4817G)
Hi From the screenshot you shared we could see the NiosV is being brought up. You could not start downloading you application file (.elf) to the device using the command "niosv-download <path to elf>" Once completed you could see the Nios V logs that are output to the jtag uart using the the command "juart-terminal" You could refer to the ED on running the HelloWorld in the link : https://www.intel.com/content/www/us/en/design-example/815406/max-10-fpga-helloworld-on-nios-v-m-processor-design-example.html For BSP setting I would suggest you to take a look at the boot method guide in the link: https://docs.altera.com/r/docs/726952/25.3/nios-v-embedded-processor-design-handbook/introduction-to-nios-v-processor-booting-methods38Views0likes1CommentRe: AshlingRISCFree IDE Build system: 'source directory does not appear to contain CMakeLists.txt"
Hi drbarryh Since this case was created regarding the RiscFree IDE Cmakelist not appearing. Is the initial issue resolved? I would suggest that we continue the TSE related discussion in the other post : https://community.altera.com/discussions/nios-system/correct-way-to-use-msgdma-with-a-niosvm-processor-on-a-max10-fpga/35079418Views1like1CommentRe: Operating system kernel-level FPGA bridge communication
Dear Customer, Since no further clarification is needed on this thread, it will be transitioned to community support for further help on doubts in this thread. Please login to the Altera Community Forum and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Thank you for the questions and as always pleasure having you here. Best Wishes Altera Tech Support17Views0likes0Comments