tehjingy_Altera
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Re: Why does the system report an error when generating rbf from sof files and fsbl files?
Hi grit One last suggest is could you remove the " ./ " in front of the u-boot-spl.hex as a final test? If that still have error could you try sharing me your sof and hex file for testing.11Views0likes0CommentsRe: Correct way to use mSGDMA with a NIOSV/m processor on a MAX10 FPGA
Hi drbarryh The link shared by SueC_Altera is the one you are looking for. It is using the NiosV processor core with the mSGDMA IP. It is for the Agilex7 but you could recreate the hardware connections in the project for the device that you want. Do take note on the naming of the par. It should be top.par and not top(x).par if you have downloaded multiple. But once you managed to unzip the par, you should go thorugh the IP Upgrade which is prompt when you open the project for the first time. In the project folder you could see a folder names "sw" in it you could see a main source that you could reference on accesssing the mSGDMA IP from the NiosV processor.7Views1like1CommentRe: Why does the system report an error when generating rbf from sof files and fsbl files?
Hi If you are using the command line below are you able to attach the fsbl to the bitstream? If not what is the error you are looking at? quartus_pfg -c stratix10-ed-gsrd/install/designs/s10_htile_soc_devkit_oobe_baseline.sof ghrd.jic \ -o device=MT25QU128 \ -o flash_loader=1SX280HU2F50E1VGAS \ -o hps_path=u-boot-socfpga/spl/u-boot-spl-dtb.hex \ -o mode=ASX4 \ -o hps=1 Is the u-boot-spl-dtb.hex in the same folder as the sof file that you are using to generate in the GUI?17Views0likes2CommentsRe: Why do I intermittently see reboot failure in the u-boot stage when running the Arria 10?
Dear Customer, Since a solution is provided and no further clarification is needed on this thread, it will be transitioned to community support for further help on doubts in this thread. Please login to the Altera Community Forum and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Thank you for the questions and as always pleasure having you here. Best Wishes Altera Tech Support7Views0likes0CommentsRe: Why do I intermittently see reboot failure in the u-boot stage when running the Arria 10?
Hi ktabacchi The the fix for this was not mentioned in the Quartus Tool Release note. The exact fix to this issue could be found in the commit ID 70bcba5 in the uboot branch below: https://github.com/altera-fpga/u-boot-socfpga/commit/70bcba5c5b2f4be77e84a6ac996b3e6d9560113c The internal bug/issue number is 16027732371.24Views0likes0CommentsRe: Why do I intermittently see reboot failure in the u-boot stage when running the Arria 10?
Hello ktabacchi This have been solved in the release of 25.3. Could you try out the u-boot version 2025.07 and linux version socfpga-6.12.33-lts? https://altera-fpga.github.io/rel-25.3/embedded-designs/arria-10/sx/soc/boot-examples/ug-linux-boot-a10-soc/ Regards tehjingy68Views0likes1CommentRe: Potential Documentation Error in ES-1057 Errata Doc: "HPS EMAC" Issue Listed for Arria 10 GX/GT
Hi Thanks for raising this issue. Yes, the HPS is only present in the Arri10 SX family and not in the GX/GT family. This will only affect the SX and not the GX/GT family. I will feedback this issue to our document collateral team. Regards tehjingy15Views1like0Comments