ContributionsMost RecentMost LikesSolutionsRe: Created Free NIOSV IP evaluation license but did not get any license file by email? Dear Customer, Since a solution is provided and no further clarification is needed on this thread, it will be transitioned to community support for further help on doubts in this thread. Please login to the Altera Community Forum and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Thank you for the questions and as always pleasure having you here. Best Wishes tehjingy Re: ERROR building simple NIOSV Compact project Hi Barry, Since no further clarification is needed on this thread, it will be transitioned to community support for further help on doubts in this thread. Please login to the Altera Community Forum and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Thank you for the questions and as always pleasure having you here. Regards Jingyang, Teh Re: ERROR building simple NIOSV Compact project Hi Barry There is a document fo the Nios V boot methods and steps on creating the project in the link below: https://www.intel.com/content/www/us/en/docs/programmable/726952/25-1/processor-hardware-system-design-with.html Regards tehjingy Re: Cyclone V HPS FPGA2SDRAM Clock Queries Hi Let me know if further assistance is needed . Do you have any follow up question from the previous comment? Regards JIngyang, Teh Re: Nios-V C++ Debug Problem Dear Customer, Since a solution is provided and no further clarification is needed on this thread, it will be transitioned to community support for further help on doubts in this thread. Please login to the Altera Community Forum and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Thank you for the questions and as always pleasure having you here. Best Wishes Altera Tech Support Re: Quartus 25.x alternative to nios2-terminal Hi, With no further clarification on this thread, it will be transitioned to community support for further help on doubts in this thread. Please login to the Altera Community Forum and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Thank you for the questions and as always pleasure having you here. Regards Jingyang,Teh Re: Cyclone V HPS FPGA2SDRAM Clock Queries Hi Brian, There is no definitive answer for the maximum frequency of the F2SDRAM bridge. For Cyclone V, F2SDRAM bridge access is managed by the SDRAM subcontroller system, and the operating frequency for the L3 Interconnect, which the F2SDRAM bridge uses has a maximum clock rate of 400 MHz for the -1V speed grade. https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/interconnect-block-diagram-80449.html https://www.intel.com/content/www/us/en/docs/programmable/683801/current/hps-clock-performance.html The available throughput is shared among all F2SDRAM bridges instantiated in the system. As more bridges are added, we will need to reduce the input frequency to ensure reliable operation and to stay within the total bandwidth limits. Please also note that the above calculation is theoretical. In practice, real-world throughput may be lower due to various system factors. Regards Jingyang, Teh Re: Cyclone V HPS FPGA2SDRAM Clock Queries Hi I am tehjingy_Altera, and I will be helping you with your issue. Does the Linux distro hang every time the f2sdram_bridge is accessed? Could you elaborate more on the behavior? Re: Cyclone V: how to boot Linux from QSPI? Hi dpeng Please refer to our User Guide for the Cylcone V Boot from QSPI. https://altera-fpga.github.io/rel-25.3/embedded-designs/cyclone-v/sx/soc/boot-examples/ug-linux-boot-cve-soc/#2-cyclone-v-soc-boot-from-qspi In the steps there are 4 different binaries that was created u-boot-with-spl.sfp, socfpga_cyclone5_socdk.dtb, zImage and core-image-minimal-cyclone5-rootfs.jffs2. These files are required to boot into the linux environment. These binaries are flashed into the QSPI Image separately into the address shown in table below: Regards tehjingy Re: Nios-V C++ Debug Problem Hi Balerion Please let me know if the provided solution resolves your issue. Regards tehjingy