Forum Discussion
ContributorCyclone V custom board VCCIO puzzling behavior
There are new measured data.
If I attached a simple 10k resistor to the 1.2V rail. it will drop back to normal 1.2 range.
But the loaded /w 10k is still measuring 40mV higher than unloaded DCDC w/o the FPGA chip.
So there are some leakage current inside the diode path? from VCCPD to VCCIO?
Super ContributorHi,
I don't yet understand the relation to "open FMC slot". Or are you feeding VCCIO externally? Unusual, but no problem according to Cyclone V hot-socketing feature.
LVDS I/O standard for Cyclone V uses 2.5 V supply, How is LVDS signal related to 1.2V VCCIO.
You have previously reported VCCPD to VCCIO leakage, there should be no relation to I/O pin leakage. Or do you suspect that VCCIO 1.2 V is raised due to I/O voltage exceeding VCCIO rather than VCCPD? In this case, I/O pin leakage can matter.
Just for clarification:
- What's the configured I/O standard in the affected I/O bank(s)?
- Are I/O pins driven externally above VCCIO?
Regards
Frank
BrianSune_FroumFirst appreciated trying to help but I guess you had tried all your best.
But with all due respect.
Your questions make me feel stupid.
FMC LPC or HPC card slot is a very standard.
I had never hear LVDS is 2.5V only.
I am afraid your comment just review you had no idea on any hardware designs nor standard.
I guess wait for vendor responses or guidance are a better choice.
