Dear Intel and all, I am working on Cyclone V soc 5CSEBA5U19C8N. There is a very puzzling VCCIO behavior. According to "Cyclone® V Device Family Pin Connection Guidelines PCG-01014-3.2". Any 3...
If I attached a simple 10k resistor to the 1.2V rail. it will drop back to normal 1.2 range. But the loaded /w 10k is still measuring 40mV higher than unloaded DCDC w/o the FPGA chip. So there are some leakage current inside the diode path? from VCCPD to VCCIO?
Very simply, just like FMC slot ->Before any slot cards are inserted to the slot it is open.
Then an open slot will introduce a voltage as this ticket mentioned.
Why waste power on unnecessary resistor when it should not be the case.
Any development board could experience such issue before the slot is use.
So unless there is a good explanation VCCIO on 1.2V or 1.5V is risky as it introduce unexpected raise of VCCIO rail.
There are no deep investigation on driver IOs in purpose of the empty slot IO bank via dummy IO on HDL design.
So far there are no official response on this issue, and I can't see this is related to any external damage like ESD etc.
As for the leakage, this is also pure guess on diode or any pass-gate whatever leakage from the beginning, but after study more documents this is not the actual case.
So applying resistor to remove the raise on voltage rail is just covering the issue without really knowing what is the problem.
Such solution is just introduce lifespan hazard.
### More document study
The group of the FMC slot is 14 sets of LVDS.
Assuming 28 * 30uA = 840uA.
Assuming 1.2V at 840uA = 1k43 ~ =1k5
But this only applied to IO undriven as input case.
If my understand is correct. the default Quartus sets the undriven IO to input /w small pull-up.
However, even setting the project to output driven to ground only makes 10mV different.
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