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BrianSune_Froum's avatar
BrianSune_Froum
Icon for Contributor rankContributor
1 year ago
Solved

Cyclone V custom board VCCIO puzzling behavior

Dear Intel and all, I am working on Cyclone V soc 5CSEBA5U19C8N. There is a very puzzling VCCIO behavior. According to "Cyclone® V Device Family Pin Connection Guidelines PCG-01014-3.2". Any 3...
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  • BrianSune_Froum's avatar
    BrianSune_Froum
    1 year ago

    There are new measured data.

    If I attached a simple 10k resistor to the 1.2V rail. it will drop back to normal 1.2 range.
    But the loaded /w 10k is still measuring 40mV higher than unloaded DCDC w/o the FPGA chip.
    So there are some leakage current inside the diode path? from VCCPD to VCCIO?

Farabi_Altera's avatar
Farabi_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hello,


1- You observed voltage increase at VCCIO power rails. How about the IO signals within the impacted VCCIO banks? Do you observed voltage increase as well?

2- Do this observation impacted any functional behavior of the device? like design failure, FPGA temperature increase etc?


regards,

Farabi


  • BrianSune_Froum's avatar
    BrianSune_Froum
    Icon for Contributor rankContributor
    1 year ago

    @Farabi

    1) yes both VCCIO and the FPGA-IO on the victim banks. However the VCCIO is higher than IO about 20-40mV.


    2) Design failure <- not fully understand, temperature increase (cannot tells because w/o HPS running the system total power is less than 1.3W)
    If needed can run a IR image to check hot spot but don't think this is helpful due to ~100mA on 12V input.
    The design had individual power rail voltage+current sense yet minimum current range is ~=0.217 mA .

    1mA is measured and print on linux hwmon, not sure this is out of range. (no extra load resistor is added as well)

    Extra info:

    Currently the DCDC is set to 1.8V no extra resistor or load show no issue.
    So it is happened on 1.5V or below VCCIO standard.