Farabi
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Re: FPP C\Cpp code reference
Hello, Unfortunately, Altera does not provide a specific code to configure FPGA from specific MCU such as STM32H7. There is method to use portable C source on JAM/STAPL and JAM Byte-code players. 1- generate .jam or .jbc from Quartus of your design, then run on STM32 using intel's JAM STAPL Player (C interpreter) or more compact Jam Byte-Code player. These players toggle TCK/TMS/TDI and sample TDO through MCU GPIOs you implement in small stub. 2- References : https://www.altera.com/design/programming/jam-support 3- References : https://cdrdv2-public.intel.com/654049/an586.pdf regards, Farabi4Views0likes0CommentsRe: Cyclone 10 GX Startup Time Support
Hello, Here are some recommendation to minimize the bootup time. 1- use fast flash - ASx4 or FPPx8 Flash is fastest 2- compress bitstream - can reduce up to 60% of original bitstream size 3- increase flash clock frequency - 100 to 166MHz if possible 4- optimize power ramp up time - VCC/VCCPT/VCCA can go as fast as 1-2ms(normal 5-10ms) while still meeting the spec 5- use Fast POR mode regards, Farabi1View0likes0CommentsRe: Does the 1SG280LU2F50E2VG support bitfile encryption
Hello, Yes, the FPGA is compatible for design encryption. If you are using the quartus_pfg command line tool to convert your AES root key .qek file into the compact certificate .ccert format. You need to specify the key storage location while creating the compact certificate. You may use the quartus_pfg tool to create an unsigned certificate for later signing. You must use a signature chain with the AES root key certificate signing permission, permission bit 6, enabled in order to successfully sign an AES root key compact certificate. 1. Create an additional key pair used to sign AES key compact certificate using one of the following command examples: quartus_sign --family=stratix10 --operation=make_private_pem \ --curve=secp384r1 aesccert1_private.pem quartus_sign --family=stratix10 --operation=make_public_pem \ aesccert1_private.pem aesccert1_public.pem pkcs11-tool --module=/usr/local/lib/softhsm/libsofthsm2.so \ --token-label s10-token --login --pin s10-token-pin \ --keypairgen –mechanism ECDSA-KEY-PAIR-GEN \ --key-type EC:secp384r1 --usage-sign --label aesccert1 --id 2 2. Create a signature chain with the correct permission bit set using one of the following commands: quartus_sign --family=stratix10 --operation=append_key \ --previous_pem=root_private.pem \ --previous_qky=root.qky \ --permission=0x40 --cancel=1 \ --input_pem=aesccert1_public.pem \ aesccert1_sign_chain.qky quartus_sign --family=stratix10 --operation=append_key --module=softHSM \ -–module_args="--token_label=s10-token \ --user_pin=s10-token-pin \ --hsm_lib=/usr/local/lib/softhsm/libsofthsm2.so" \ --previous_keyname=root \ --previous_qky=root.qky \ --permission=0x40 --cancel=1 \ --input_keyname=aesccert1 \ aesccert1_sign_chain.qky regards, Farabi0Views0likes0CommentsRe: Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)
Hello, On Cyclone 10GX, the device does not immediately enter user mode after configuration. In datasheet: tCD2UM is around 175us to 830us. The root cause of your failure migt be caused by you are reading the Remote Update Registers before the device has entered User mode. Recommendation - you must not interact with user logic until INIT_DONE goes high. The all 1's you are observing is expected when reading any uninitialized Avalon-MM register space. regards, Farabi21Views0likes0Comments