Farabi_Altera
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Re: Cold Temperature Issue
Hi Asaf, Before reheating the FPGA at assembly house - power up successful After reheating the FPGA at assembly house - power up fail Is above statement correct? My question : 1- How many boards fail? how many boards pass? 2- what is the purpose of re-heating at assembly house? 3- Is it possible to check solder cracks using xray? 4- nSTATUS not rising meaning device not starting configuration- still in reset mode. Can you check power rails are stable? VCC, VCCIO_SDM etc regards, Farabi0Views0likes0CommentsRe: Power and thermal characterization of Agilex 5
Hello Chris, 1- Power analyzer partitions device power into categories. Some infrastructure power may be allocated to DSP or RAM category even though no DSP arithmetic or memory read/write activity is occurring. 2- Even individual blocks are power-gated, the surrounding clocking and infrastructure networks still exist on the die. The analyzer may distribute a portion of this activity into DSP/RAM categories. 3- Power Analyzer includes small baseline dynamic values to account for device-level activity that cannot be cleanly assigned elsewhere. In nearly empty design, these baseline values can appear in the calcualtion. regards, Farabi9Views0likes0CommentsRe: Power and thermal characterization of Agilex 5
Hello Chris, 1- Typical static power model i- When the typical static power model will be available? Ans: Please refer here Table 23 ii- access to pre-release model Ans: All the E-series power model is updated in 26.1 2- Power and Thermal Analyzer on empty design i(a)- design use no DSP or RAM blocks Ans: This is expected. Even no DSP or M20K blocks instantiated, the silicon physically contributes leakage/static power. i(b)- Which fabric component draw power significantly Ans: clock input buffer, Global clock, configuration related circuitry, SDM, default termination, unused IO bank static leakage etc.IO is only one part of the contributors. i(c) - what is included in miscellaneous category? Ans: SDM related circuit, Configuration circuit, Device management logic, power-monitoring circuit(POR), temperature/voltage sensing circuit, etc. 3- Can HPS and transceivers by fully powered down by disconnecting the power rails? Ans: Basically yes, but why? you can choose device variance without HPS and without transceiver if you dont want this feature. This variance comes without HPS and transceivers. regards, Farabi0Views0likes3CommentsRe: Quartus 26.1: quartus_asm triggers quartus_pfg despite disabled generation flags
OK, Reproduction: Run repeatedly without changing anything: quartus_asm <proj> --read_settings_files=on --write_settings_files=off -c <rev> --set=GENERATE_PROGRAMMING_FILES=OFF --set=GENERATE_RBF_FILE=OFF I will run above and will update the result.15Views0likes0Comments