Farabi
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Re: Manual checksum verification of CFM0
Hello, There might be some confusion here: Checksum : configuration data checksum, reflect the contents that actually downloaded/configured into CFM. Any changes to the bitstream will change checksum. Usage to detect corruption or mismatch in configuration data. Usercode : it is NOT the checksum of the POF file. Quartus may default it to something static or left constant. Usercode remains identical is expected behavior. Usage to version tagging/design identification/JTAG bases system identification. regards, Farabi0Views0likes0CommentsRe: Why does PTA show zero W for F-tiles in Hierarchical Design Editor
Hello, You need to run full compilation and assign all pins correctly, then PTA will show the correct power report. I tried in Altera environment and can see all the power rails reported correctly. regards, Farabi34Views0likes0CommentsRe: Quartus 26.1: quartus_asm triggers quartus_pfg despite disabled generation flags
Hello, From what I understand, even you explicitly disabled to generate programming files below : quartus_asm <proj> --read_settings_files=on --write_settings_files=off -c <rev> --set=GENERATE_PROGRAMMING_FILES=OFF --set=GENERATE_RBF_FILE=OFF after compilation, quartus_asm still generates the .sof and .rbf. I can replicate this in Quartus Pro 26.1. I am filing ticket to SW engineering to look into this. regards, Farabi4Views1like0CommentsRe: Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)
Hello Sumanth, I can make below conclusion: 10CX105YF672I5G – industrial grade RSU working as normal 10CX150YF672E5G – enhanced grade required 300us delay to make RSU working The only difference between -I and -E is the package temperature support. No difference in the silicon. You are using same design, same hardware setup, same bitstream image. You only see the delay at 1 unit. This is very difficult to make conclusion. Next step: 1- Are you able to swap the unit with known working board? 2- Are you open to send the unit for FA? regards, Farabi0Views0likes0CommentsRe: Agilex 5 configuration via Avalon-ST x8 issues
Hello, Please make sure below connection are implemented: 1- nCONFIG pull up to VCCIO_SDM via 10kOhm resistor 2- nSTATUS pullup to VCCIO_SDM via 10kOhm resistor 3- CONF_DONE is based on your selection of SDM IO pin, default SDM_IO16. If you select other than SDM_IO0 or SDMIO16, you need to connect external 4.7kOhm pulldown resistor to this pin. regards, Farabi0Views0likes0CommentsRe: Power-Down Sequence Requirements for the Agilex 7 F-Series(2x F-Tile) Devices
Hello Deva, If the power down ~1sec, its too slow. Basically power down sequence is just the reverse of power up sequence. Please make all the power rails ramping down not more than 100ms. regards, Farabi5Views0likes0CommentsRe: Quartus and power domain
Hello, The temperature increase is happening before configuration. This is abnormal elevated leakage in part of the die. Definitely not dynamic switching power. Are you seeing this behavior at only 1 unit? Next step: 1-can you try power up with slower ramp time? (within timing spec) 2- how many boards manufactured? All showing same behavior? 3- Is it possible to swap unit on the board with another one? - to see if the issue follows unit or follows board 4- Please send snap shot of the device top marking so I can analysia the production test history. regards, Farabi7Views0likes0Comments