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Re: Can Agilex 3 A3CY100BM16AE7S (AXC3000) use SDM cryptographic services?
Hello, Question 1: Does spec code Y support SDM Cryptographic Primitive Services? Yes — per the authoritative Security Technical Reference Manual, it does. The Security TRM explicitly groups Agilex 3 devices W and Y together: Cryptographic Primitive Services = Yes, while only the Z variant is listed as No. Security Technical Reference Manual The full W/Y feature row confirms: SDM Version 1.5; Cryptographic Primitive Services = Yes; Black Key Provisioning = SPDM; Attestation Support = SPDM 1.2; Secure Data Object Storage = Yes. Hard Processor System Technical Reference Manual The C-Series Product Table (SUPPLEMENTARY) appears to show Y=No for "Crypto," which contradicts the Security TRM. The Security TRM is the higher-authority source and takes precedence. That conflict is worth noting, but the decisive document is unambiguous: spec Y is in the same capability tier as W for cryptographic primitive services. On the Mailbox Client IP side, the cryptographic offloading feature is available for Agilex 7, Agilex 5, and Agilex 3 devices in Quartus Prime Pro Edition version 21.3 or later, Enabling Cryptographic Services and specifically for Agilex 3 devices, this feature is available in Quartus Prime Pro Edition version 25.1 or later. Mailbox Client IPs User Guide Your 26.1 build satisfies that requirement. Question 2: Is 0x085 the expected response, or should it be 0x0F? Given that your device (spec Y) does have the hardware capability, 0x085 is the more informative and correct rejection. Error 0x0F would mean "function not supported on this device" — a hard silicon limitation. Error 0x085 is in the command-specific error range (0x80–0x8F), which indicates a command-specific error due to an SDM command you used. Error Code Responses The interpretation you found in the Security TRM — "command not allowed under the current security settings" — is consistent with a device that has the capability but has a security policy or provisioning gate blocking access. You'd only expect 0x0F on a Z-variant device. Question 3: What could cause 0x085 on a capable device? The root cause is almost certainly a provisioning or security policy prerequisite not being met. Key factors to check: SDM security provisioning state: The foundational element of the security architecture is the SDM — a self-contained system-on-chip that securely manages boot, provides secure key storage, and enforces security policies. Security Overview for SDM-Based FPGA Devices Cryptographic primitive services are governed by those same enforced policies. If the device has not been provisioned with the required credentials (key hierarchy, owner root key, or SPDM identity), the SDM will reject crypto service session open commands at the policy enforcement layer. SPDM/Black Key Provisioning requirement: For W/Y devices, Black Key Provisioning is via SPDM. Hard Processor System Technical Reference Manual If SPDM-based provisioning has not been completed, the SDM may deny crypto service access regardless of the Enable Crypto Service IP parameter setting. SDM crypto engines availability during user mode: The SDM contains hardened cryptographic acceleration engines. When not in use by the SDM for configuration, they are made available to the FPGA design or HPS software through the SDM mailbox interface while the FPGA is in user mode. Security Overview for SDM-Based FPGA Devices If there is any active SDM internal use or policy restriction, access is blocked. Mailbox Client instantiation limit: For Agilex 5 and Agilex 3 devices, only one instantiation of the Mailbox Client IP is supported. Mailbox Client IPs User Guide Verify your design has exactly one instance. Response FIFO management: Ensure that you read or flush out the content in the response FIFO before issuing a new command. Continuously sending commands without reading back valid data from the response FIFO gradually fills it. When the response FIFO overflows, the SDM freezes. Mailbox Client IPs User Guide Your test methodology (reading response FIFO after each command) looks correct for this. Question 4: Is there a supported way to enable these services? The IP parameter side is already correctly configured — setting Enable Crypto Service to 1 in the IP parameter editor causes the Mailbox Client IP to generate a 64-bit AXI manager interface used to pass data between the cryptographic fabric IP and user space memory. Mailbox Client IPs User Guide That part is right. The blocker is almost certainly on the SDM provisioning side. For detailed Cryptographic Services Mailbox Command descriptions, refer to the Security Methodology for Altera FPGAs and Structured ASICs User Guide, which contains detailed descriptions of security features and technologies to help you select the security features necessary to meet your security objectives. Mailbox Client IPs User Guide For more information or access, contact Altera Premier Support and quote ID #14014613136. Mailbox Client IPs User Guide That document (NDA-gated) covers the exact provisioning workflow required before open_crypto_service_session will succeed. In summary: your A3CY100BM16AE7S (spec Y) is documented as capable of SDM cryptographic primitive services; the 0x085 response confirms the SDM is rejecting the command on policy/provisioning grounds, not on a silicon capability limitation. The next step is to work through the SDM provisioning flow described in the Security Methodology User Guide for your device. regards, Farabi0Views0likes1CommentRe: 3.3 V Connection to ADC_VREF When Replacing a MAX 10 SC Device with an SA Device
Hello, this is a very common concern when swapping between SC and SA variants in the same package. What the Pin Connection Guidelines say: The ADC_VREF pin is the ADC voltage reference input. The guidelines state you should tie it to an external accurate voltage reference source; if you are not using the external reference, this pin should be left as no connect (NC). MAX 10 FPGA Device Family Pin Connection Guidelines That is the formal recommendation. However, looking at the electrical specs for this specific scenario: Electrical impact of connecting 3.3 V to ADC_VREF: The ADC_VREF pin leakage current in single supply mode has a maximum of 10 µA. MAX 10 FPGA Device Datasheet Since the 10M08SAU169C8G is a single-supply SA device, this is the applicable spec. Connecting 3.3 V to ADC_VREF will source at most 10 µA from your 3.3 V rail — that is the only electrical load imposed on that net. For single-supply devices, the external reference voltage can be up to 3.63 V. Modular ADC Core Parameters Settings 3.3 V is comfortably within this range, so the voltage level itself is not out-of-spec for that pin. Functional impact if the ADC is not used: Each ADC block in MAX 10 devices can independently use an internal or external voltage reference. MAX 10 Analog to Digital Converter User Guide If you do not instantiate the ADC IP in your design and select the internal reference (or simply leave the ADC unused), the ADC_VREF pin being driven to 3.3 V will not affect FPGA fabric logic operation. The pin will simply present a leakage load as noted above. Bottom line: From a pure electrical standpoint, 3.3 V on ADC_VREF is within the single-supply device's specified pin voltage range, and the only consequence is a ≤10 µA leakage draw. The NC recommendation in the Pin Connection Guidelines is the conservative design practice when the external reference is intentionally unused — it is not an absolute prohibition against having a voltage present on the pin. If your design does not instantiate the ADC or does not select external VREF, device functionality should not be affected. That said, the formal guideline does say NC for the unused-reference case, so if your design review process or qualification requirements mandate strict adherence to the Pin Connection Guidelines, a PCB revision to add a DNP (do-not-populate) series resistor or leave the trace open would be the fully compliant path. For most applications, however, the 3.3 V connection as-is is electrically benign for this pin on the SA single-supply variant. regards, Farabi3Views0likes0CommentsRe: reduced VCCL_SDM, VCCPLLDIG_SDM on A5E
Hi Glen — let me address both points. Power estimation tool at this stage (no Quartus design yet) The Altera power analysis features, including the Power and Thermal Calculator (PTC) and the Quartus Prime Power Analyzer, give you the ability to estimate power consumption from early design concept through design implementation. Power Management User Guide The PTC can be used at any time — including before you have a design. For post-fit power analysis, you get better results with the Quartus Prime Power Analyzer, which is a post-fit tool only. Power Management User Guide The PTC calculates the power consumption of an Agilex 5 FPGA and generates thermal parameters needed for system thermal simulation or evaluation of a cooling design. There are two versions: a standalone version that you can use without an actual RTL design, where you provide all input manually. The standalone version is essential at the early stages of projects when power and cooling requirements must be determined and no RTL design is yet available. Power and Thermal Calculator (PTC) The accuracy of the PTC is rated as medium. Power Management User Guide Note that static power consumption is not the same for every part — the distribution across a given lot is more like a bell curve, but the PTC reports the highest static power for each part, so your cooling and power system can encompass all parts. Thermal Design User Guide: Agilex™ 5 FPGAs and SoCs Once you do have a compiled design, Altera recommends switching from the PTC to the Power Analyzer in Quartus Prime, as the Power Analyzer produces more accurate results because it has more detailed information about your design. Power Management User Guide --- Static power comparison: –2V vs –6X This is the critical point here, and the answer may actually be the reverse of what you're expecting: The –2V is a SmartVID standard-power device, while the –6X belongs to E-Series Device Group B, which is a fixed voltage, power-optimized device. The E-Series Device Group B fixed voltage devices support 0.75 V, 0.78 V, and 0.8 V. Using a fixed low core voltage, they further reduce total power consumption — and these fixed voltage devices have lower static power than the SmartVID standard power devices while maintaining device performance. Agilex® 5 FPGAs and SoCs Device Overview So if minimizing static power is a priority, the –6X (fixed voltage, Group B) is actually the lower static power option compared to the –2V (SmartVID standard power). The PTC is the right tool to quantify this difference at your current pre-design stage — run it for both speed/power grade options with your expected resource utilization estimates to get a side-by-side static power comparison. regards, Farabi5Views1like1CommentRe: reduced VCCL_SDM, VCCPLLDIG_SDM on A5E
Hi Glen, --- Part 1 — Tying VCCL_SDM / VCCPLLDIG_SDM to VCCcore on –2V / –3V devices The short answer is: this is out-of-spec operation and the documentation does not characterize the failure modes, but I can give you the full context of why it's problematic. The Pin Connection Guidelines are unambiguous about the required supply voltage for VCCL_SDM: VCCL_SDM is the SDM power supply. For devices with speed grade –1V, –2V, –2E, –3V, and –4S, these pins must be connected to a 0.8-V power supply. Pin Connection Guidelines The guidelines further state to connect VCCL_SDM to a dedicated 0.8-V power supply. Pin Connection Guidelines And for VCCPLLDIG_SDM specifically: VCCPLLDIG_SDM must be sourced from the same regulator as VCCL_SDM, with proper isolation filtering. Pin Connection Guidelines On –2V and –3V SmartVID devices, VCCcore is PMBus-controlled and will be actively pulled down during the ITD (Initial Trim and Detect) phase and thereafter to the optimal operating point — it is not fixed at 0.8V. Agilex 5 SmartVID standard power devices must be driven by a PMBus-compliant voltage regulator operating in either PMBus master or PMBus slave mode. Power Management User Guide The core voltage is explicitly dynamic. Tying VCCL_SDM to VCCcore means the SDM's own supply rail will track those voltage commands. At 0.725V or 0.7V, VCCL_SDM would be well below the 0.8V ±3% (≈0.776V minimum) requirement for –2V/–3V parts. Your intuition about SDM operation and PLL behaviour being impacted is correct in principle — the SDM controls configuration, security, and boot, and VCCPLLDIG_SDM powers the SDM's PLL — but the available Pin Connection Guidelines and Power Management documentation do not characterize the specific failure modes or frequency de-rating at those sub-spec voltages. I cannot give you a documented "PLL F max breaks at X mV" figure for VCCL_SDM, as that is not published. What is documented is that the rail has a hard requirement for 0.8V for these speed grades, and operating below it is unsupported. One practical note: you do have the option to connect VCCL_SDM, VCC_HSSI, VCC_IO_SDM, and VCCL_ADC_SDM to the same regulator as VCCPLLDIG2_HPS VCC and VCCP when the power rails require the same voltage level, and you may also connect VCCPLLDIG1_HPS, VCCPLLDIG2_HPS, and VCCPLLDIG_SDM to shared VCC, VCCP, and VCCL_HPS power planes with proper isolation filtering. Pin Connection Guidelines This sharing is permitted when those rails are at the same level — but that level must still be 0.8V for –2V/–3V devices. It doesn't eliminate the separate 0.8V requirement; it just allows regulator sharing with proper filtering. --- Part 2 — Varying VCCcore voltage in the PTA for static power analysis The Power and Thermal Calculator for Agilex 5 devices provides a current and power estimate based on various conditions such as room temperature and nominal voltage. Power Management User Guide The Power and Thermal Calculator results for Agilex 5 devices are based on preliminary simulated data. Power Management User Guide The PTA Tcl API (the ::quartus::pta package) exposes edit , get_results , recalculate_power , and related commands for modifying resource-level parameters (e.g. RAM block count, clock frequency, enable percentage). However, the documented PTA Tcl properties visible in the available documentation are design-resource-level inputs — there is no documented edit property key for sweeping VCCcore or VCCL_SDM voltage to characterise static power versus supply voltage in the current PTA model. The calculator works at nominal voltage. For post-fit analysis, Altera recommends switching from the Power and Thermal Calculator to the Power Analyzer in Quartus Prime once your design is available, because the Power Analyzer produces more accurate results — it has more detailed information about your design, including routing and configuration information about all the resources in your design. Power Management User Guide Agilex™ 5 FPGAs and SoCs The Quartus Prime Power Analyzer does have voltage/temperature corner options in the Power Analysis settings (Process, Voltage, Temperature — PVT), which is the proper place to explore static power sensitivity to supply voltage. That's the tool to reach for if you want to model reduced VCC static power at lower activity states; the standalone PTA is not the right vehicle for a VCC sweep. In terms of your broader goal of reducing static power at low activity: the SmartVID feature compensates for process variation by narrowing the process distribution using voltage adaptation, Power Management User Guide which is the primary mechanism for VCC reduction on –1V through –3V parts. Reducing clock frequencies will cut dynamic power directly, but static power reduction is best modelled in Quartus Prime Pro's Power Analyzer with appropriate PVT corner settings. rgards Farabi0Views1like0CommentsRe: Cyclone 10 GX AS x4 Configuration Compatibility with Infineon S25FS512S (Custom Flash Definition)
Hello Sumanth, I can't reply in my system due to long answer(system limitation- this will be fixed in future), so I will reply here in community: Hello Sumanth, Thank you for providing the detailed logic analyzer observations and test environment context. Below are the clarifications and answers to your questions regarding the Cyclone 10 GX Active Serial x4 (AS x4) configuration behavior with the Infineon S25FS512S flash. 1. Does the Cyclone 10 GX configuration controller support transmitting the mandatory Mode Byte required by the EBh (Quad I/O Read) command? No. The Cyclone 10 GX hard configuration controller (Control Block) does not generate or transmit a separate Mode Byte (also known as continuous read / XIP bits, M[7:0]) during the 0xEB (Quad I/O Fast Read) command sequence. During Active Serial x4 configuration, the hardwired state machine inside the Cyclone 10 GX Control Block issues the following standard read transaction: Opcode: 0xEB (1 line, 8 clock cycles) Address: 4-byte / 32-bit address (4 lines, 8 clock cycles) Dummy Clock Cycles: Fixed/configured clock cycles on DCLK (the FPGA does not drive active mode bits during these cycles) Data Phase: Reads configuration bitstream data on DATA[3:0] Because the FPGA configuration controller treats the cycles immediately following the address purely as wait/dummy cycles, it does not transmit the 8-bit mode byte pattern (M[7:0], which occupies 2 clock cycles across 4 I/O lines) required by the Infineon S25FS512S protocol. 2. Is this a known limitation of the Cyclone 10 GX configuration controller or Quartus Programmer? This is a hardware controller architectural characteristic/limitation of the Cyclone 10 GX Control Block, not a limitation of the Quartus Programmer tool. The Quartus Programmer is solely responsible for generating the programming image (.jic / .rpd) and programming the flash via JTAG using the Serial Flash Loader (SFL) IP. Once programming is complete and the FPGA initiates configuration (upon power-up or nCONFIG pulse), the hard configuration engine in the Cyclone 10 GX acts as the SPI master. The Cyclone 10 GX configuration controller was architected based on standard SPI NOR protocols (such as Micron and EPCQ-L devices), where random reads do not require a separate mode byte between the address and dummy clock cycles. On the Infineon S25FS512S, the 0xEB command expects 2 mode cycles (8 bits on 4 lines) immediately following the address, followed by the programmed dummy/latency cycles. When the FPGA does not explicitly drive these mode cycles, the flash interprets the initial clock cycles differently or delays valid data output by 2 clock cycles relative to what the FPGA controller expects, resulting in bitstream misalignment and configuration failure. 3. Is there any supported method to modify the Quad I/O Read command sequence in the Custom Flash Definition? No. The Custom Flash Definition XML file (used in the Quartus Programmer and Convert Programming Files based on AN229767 and Altera application notes) defines the JTAG programming parameters for the SFL IP (e.g., initialization sequences, register writes, page programming, sector erase, and verification). It cannot modify, patch, or reprogram the hardwired configuration controller state machine inside the Cyclone 10 GX silicon. The read opcode (0x0B for AS x1, 0xEB for AS x4) and the protocol sequence issued by the FPGA during configuration are fixed in hardware. 4. Has Altera validated any Custom Flash Definition for the S25FS512S that can be shared as a reference? Altera has not officially validated the Infineon/Cypress S25FS512S for Cyclone 10 GX Active Serial x4 configuration. However, Altera provides a validated reference implementation for the newer Infineon/Cypress Semper family—specifically the Cypress S25HS512T with Cyclone 10 GX—in AN 1013: Using Generic QSPI Flash on Control Block-Based Devices (Section 6.1). While the S25HS512T uses standard WRSR (0x01) register programming rather than WRAR (0x71), the configuration requirements outlined in AN 1013 apply to all control block-based devices using 1.8V 512Mb flash: Key Technical Requirements & Recommendations Disable EPCS/EPCQ ID Check (Mandatory): In the Quartus Convert Programming Files tool, navigate to Advanced Options and enable "Disable EPCS/EPCQ ID check". If this check is not disabled, the Cyclone 10 GX configuration controller expects an Altera-specific Silicon ID and aborts configuration after reading the JEDEC ID (0x9F), even if the flash is correctly programmed. Dummy Clock Compensation Formula: In the Infineon S25FS512S, the 0xEB command requires 2 Mode cycles (8 bits over 4 lines) followed by $N$ latency cycles configured in CR2NV[3:0]. To account for the 2 mode cycles when configuring Convert Programming Files: $$\text{Quad I/O Dummy Clocks} = \text{Flash Latency Cycles} + 2$$ For example, if CR2NV[3:0] is set to 8 latency cycles, the Quad I/O mode dummy clock parameter in Convert Programming Files must be set to 10. If CR2NV[3:0] is set to 6 latency cycles, the dummy clock setting should be 8. Non-Volatile Register Settings for S25FS512S: CR1NV = 0x02: Enables Quad I/O (QUAD bit = 1). CR2NV = 0x88: Enables 4-byte addressing on power-up (bit 7 = 1) and sets latency code to 8 cycles (CR2NV[3:0] = 1000b), while keeping QPI disabled (bit 6 = 0). Note: Cyclone 10 GX requires 4-byte addressing upon power-up for flash densities >128 Mb (AN 1013, Section 3.2.2). CR3NV = 0x08: Configures uniform 256-KB sector architecture (UNHYSA bit = 1) to eliminate hybrid 4-KB parameter sectors. Recommended Workarounds / Path Forward: Use Active Serial x1 (AS x1): Because AS x1 uses standard Fast Read (0x0B) with 8 dummy cycles and does not require mode cycles, it is fully compatible with the S25FS512S and avoids the Quad I/O mode byte incompatibility. Supported Flash Alternatives: For applications requiring full Active Serial x4 bandwidth and guaranteed compatibility, consider selecting a tested third-party flash device from the Altera Device Configuration Support Center, such as the Cypress S25HS512T (documented in AN 1013) or supported Micron MT25QU / Macronix devices. Best regards, Farabi0Views1like0CommentsRe: Request of private case
Hello, 1. Programming files are device-specific — recompilation is required for a different density target The configuration data in a Cyclone V SE programming file (.sof, .pof, .rbf) is generated by Quartus Prime for a specific device member code. The clock source selection for the RCLK select block is controlled statically using configuration bit settings in the configuration file (.sof or .pof) generated by Quartus Prime. Cyclone V Device Handbook Volume 1: Device Interfaces and Integration Similarly, when a clock network is powered down, all the logic fed by it enters off-state; unused GCLK, RCLK, and PCLK networks are automatically powered down through configuration bit settings in the .sof or .pof generated by Quartus Prime. Cyclone V Device Handbook Volume 1: Device Interfaces and Integration These device-specific configuration bit fields mean the bitstream is structurally tailored to the exact target device's resources and routing — an A2-targeted file does not describe the larger fabric of an A5 or A7. 2. Each density variant has a unique IDCODE — and this is checked at configuration time The Cyclone V SE density variants carry distinct IDCODE part-number fields. For Cyclone V SE, the 32-bit IDCODE Part Number bits differ across member codes: A4 = 0010 1101 0000 0001, A5 = 0010 1101 0001 0010, A6 = 0010 1101 0000 0010. Cyclone V Device Handbook Volume 1: Device Interfaces and Integration These are not the same — the A2 member code similarly has its own unique IDCODE. During JTAG configuration, the IDCODE instruction identifies devices in a JTAG chain; when IDCODE is selected, the device identification register is loaded with the 32-bit vendor-defined identification code, which is placed between TDI and TDO to allow serial shifting out of TDO. IDCODE is the default instruction at power-up and in the TAP RESET state. Cyclone V Device Handbook Volume 1: Device Interfaces and Integration This means the programmer will read the physical device's IDCODE at the start of configuration and compare it against the target encoded in the programming file. A mismatch (e.g., A2 file → A5 device) will be caught at this stage. That said, the IDCODE check is not the only enforcement mechanism — the configuration data itself is structurally incompatible across densities because the fabric resources (ALMs, M10K blocks, DSP blocks, routing) are categorically different between, say, an A2 and an A5. Even if you were to bypass the IDCODE check, the bitstream would not correctly configure a device with a different resource count. 3. "Vertical migration" in Cyclone V SE is a PCB/pin-compatibility feature — not programming-file portability Altera's documented "vertical migration" capability for Cyclone V SE is specifically about I/O pin and PCB footprint reuse across densities, not about bitstream reuse. Vertical migration is supported in the U672 packages of Cyclone V SE and SX devices; however, vertical migration between these devices was disabled in Quartus II 13.0 SP1 and earlier software. To enable it, install patch 1.33 for Quartus II 13.0 SP1. Vertical migration is enabled in Quartus II version 13.1 and above. Is vertical migration supported in Cyclone V SoC devices? The intent of this feature is to allow the same PCB to accommodate different densities — you still recompile Quartus Prime targeting the specific density member code you are populating. To enable vertical migration support for Cyclone V SX and SE devices in Quartus II software version 13.0 SP1, download and install patch 1.31 (available for Windows and Linux). Cyclone V Device Handbook Volume 1: Device Interfaces and Integration To check what is pin-compatible across densities, use the Pin Migration View in the Quartus Prime Pin Planner. Cyclone V Device Handbook Volume 1: Device Interfaces and Integration 4. ES vs. production incompatibility is explicitly documented As a related compatibility note: you cannot use a Cyclone V ES configuration file to program a Cyclone V production device. Can I use a Cyclone V ES configuration file to program a Cyclone V production device? This is a separate (but illustrative) restriction showing that Altera explicitly enforces programming file compatibility boundaries and documents them when they exist. Summary A .sof/.pof/.rbf compiled for Cyclone V SE A2 cannot be programmed into an A5 or A7 without recompilation. The configuration data is device-specific, and the IDCODE encoded in the file will not match the target device's IDCODE. The IDCODE check during JTAG configuration enforces this, but the bitstream incompatibility is deeper — the configuration fabric description itself is different. Vertical migration in Cyclone V SE addresses PCB pin footprint reuse across densities, not bitstream portability. Recompile your design in Quartus Prime targeting the specific member code (A2, A5, A7, etc.) you intend to program.0Views1like0CommentsRe: Cyclone 10 GX AS x4 Configuration Compatibility with Infineon S25FS512S (Custom Flash Definition)
Hello Sumanth, Thank you for providing the detailed logic analyzer observations and test environment context. Below are the clarifications and answers to your questions regarding the Cyclone 10 GX Active Serial x4 (AS x4) configuration behavior with the Infineon S25FS512S flash. 1. Does the Cyclone 10 GX configuration controller support transmitting the mandatory Mode Byte required by the EBh (Quad I/O Read) command? No. The Cyclone 10 GX hard configuration controller (Control Block) does not generate or transmit a separate Mode Byte (also known as continuous read / XIP bits, M[7:0]) during the 0xEB (Quad I/O Fast Read) command sequence. During Active Serial x4 configuration, the hardwired state machine inside the Cyclone 10 GX Control Block issues the following standard read transaction: Opcode: 0xEB (1 line, 8 clock cycles) Address: 4-byte / 32-bit address (4 lines, 8 clock cycles) Dummy Clock Cycles: Fixed/configured clock cycles on DCLK (the FPGA does not drive active mode bits during these cycles) Data Phase: Reads configuration bitstream data on DATA[3:0] Because the FPGA configuration controller treats the cycles immediately following the address purely as wait/dummy cycles, it does not transmit the 8-bit mode byte pattern (M[7:0], which occupies 2 clock cycles across 4 I/O lines) required by the Infineon S25FS512S protocol. 2. Is this a known limitation of the Cyclone 10 GX configuration controller or Quartus Programmer? This is a hardware controller architectural characteristic/limitation of the Cyclone 10 GX Control Block, not a limitation of the Quartus Programmer tool. The Quartus Programmer is solely responsible for generating the programming image (.jic / .rpd) and programming the flash via JTAG using the Serial Flash Loader (SFL) IP. Once programming is complete and the FPGA initiates configuration (upon power-up or nCONFIG pulse), the hard configuration engine in the Cyclone 10 GX acts as the SPI master. The Cyclone 10 GX configuration controller was architected based on standard SPI NOR protocols (such as Micron and EPCQ-L devices), where random reads do not require a separate mode byte between the address and dummy clock cycles. On the Infineon S25FS512S, the 0xEB command expects 2 mode cycles (8 bits on 4 lines) immediately following the address, followed by the programmed dummy/latency cycles. When the FPGA does not explicitly drive these mode cycles, the flash interprets the initial clock cycles differently or delays valid data output by 2 clock cycles relative to what the FPGA controller expects, resulting in bitstream misalignment and configuration failure. 3. Is there any supported method to modify the Quad I/O Read command sequence in the Custom Flash Definition? No. The Custom Flash Definition XML file (used in the Quartus Programmer and Convert Programming Files based on AN229767 and Altera application notes) defines the JTAG programming parameters for the SFL IP (e.g., initialization sequences, register writes, page programming, sector erase, and verification). It cannot modify, patch, or reprogram the hardwired configuration controller state machine inside the Cyclone 10 GX silicon. The read opcode (0x0B for AS x1, 0xEB for AS x4) and the protocol sequence issued by the FPGA during configuration are fixed in hardware. 4. Has Altera validated any Custom Flash Definition for the S25FS512S that can be shared as a reference? Altera has not officially validated the Infineon/Cypress S25FS512S for Cyclone 10 GX Active Serial x4 configuration. However, Altera provides a validated reference implementation for the newer Infineon/Cypress Semper family—specifically the Cypress S25HS512T with Cyclone 10 GX—in AN 1013: Using Generic QSPI Flash on Control Block-Based Devices (Section 6.1). While the S25HS512T uses standard WRSR (0x01) register programming rather than WRAR (0x71), the configuration requirements outlined in AN 1013 apply to all control block-based devices using 1.8V 512Mb flash: Key Technical Requirements & Recommendations Disable EPCS/EPCQ ID Check (Mandatory): In the Quartus Convert Programming Files tool, navigate to Advanced Options and enable "Disable EPCS/EPCQ ID check". If this check is not disabled, the Cyclone 10 GX configuration controller expects an Altera-specific Silicon ID and aborts configuration after reading the JEDEC ID (0x9F), even if the flash is correctly programmed. Dummy Clock Compensation Formula: In the Infineon S25FS512S, the 0xEB command requires 2 Mode cycles (8 bits over 4 lines) followed by $N$ latency cycles configured in CR2NV[3:0]. To account for the 2 mode cycles when configuring Convert Programming Files: $$\text{Quad I/O Dummy Clocks} = \text{Flash Latency Cycles} + 2$$ For example, if CR2NV[3:0] is set to 8 latency cycles, the Quad I/O mode dummy clock parameter in Convert Programming Files must be set to 10. If CR2NV[3:0] is set to 6 latency cycles, the dummy clock setting should be 8. Non-Volatile Register Settings for S25FS512S: CR1NV = 0x02: Enables Quad I/O (QUAD bit = 1). CR2NV = 0x88: Enables 4-byte addressing on power-up (bit 7 = 1) and sets latency code to 8 cycles (CR2NV[3:0] = 1000b), while keeping QPI disabled (bit 6 = 0). Note: Cyclone 10 GX requires 4-byte addressing upon power-up for flash densities >128 Mb (AN 1013, Section 3.2.2). CR3NV = 0x08: Configures uniform 256-KB sector architecture (UNHYSA bit = 1) to eliminate hybrid 4-KB parameter sectors. Recommended Workarounds / Path Forward: Use Active Serial x1 (AS x1): Because AS x1 uses standard Fast Read (0x0B) with 8 dummy cycles and does not require mode cycles, it is fully compatible with the S25FS512S and avoids the Quad I/O mode byte incompatibility. Supported Flash Alternatives: For applications requiring full Active Serial x4 bandwidth and guaranteed compatibility, consider selecting a tested third-party flash device from the Altera Device Configuration Support Center, such as the Cypress S25HS512T (documented in AN 1013) or supported Micron MT25QU / Macronix devices. Best regards, Farabi0Views0likes0Comments