ContributorCustom board on Cyclone V SoC HPS SDRAM topology unclear
Dear Intel and All,
This is Brian, I am working on a C5 SoC project.
According to document "emi_plan-683385-666390.pdf"
"Leveling circuitry is dedicated I/O circuitry to provide calibration support for fly-by
address and command networks. For DDR3, leveling is always invoked, whether the
interface targets a DIMM or a single component. For DDR3 implementations at higher
frequencies, a fly-by topology is recommended for optimal performance. For DDR2,
leveling circuitry is invoked automatically for frequencies above 240 MHz; no leveling
is used for frequencies below 240 MHz.
For DDR2 at frequencies below 240 MHz, you should use a tree-style layout. For
frequencies above 240 MHz, you can choose either a leveled or balanced-T or Y
topology, as the leveled PHY calibrates to either implementation. Regardless of
protocol, for devices without a levelling block—such as Arria II GZ, Arria V, and
Cyclone V—a balanced-T PCB topology for address/command/clock must be used
because fly-by topology is not supported.
For details about leveling delay chains, consult"
This is making me very puzzling about do DDR3 Fly-by is allowed or not?
Hi Brian,
"So simply said HPS hard EMI also this rules?"
- Yes the HPS EMIF IP also same.
"So basically the entire cyclone V family do not allow fly-by topology as leveling is not included?"
- Yes, it's not supporting DDR3 SDRAM fly-by topology
"DDR3 speed is above 300MHz so do this also applying the same leveling constraints "ON HPS hard EMI"? "
- Yes
Regards,
Adzim
