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BrianSune_Froum's avatar
BrianSune_Froum
Icon for Contributor rankContributor
7 months ago
Solved

Custom board on Cyclone V SoC HPS SDRAM topology unclear

Dear Intel and All, This is Brian, I am working on a C5 SoC project. According to document "emi_plan-683385-666390.pdf" "Leveling circuitry is dedicated I/O circuitry to provide calibration supp...
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  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    7 months ago

    Hi Brian,


    "So simply said HPS hard EMI also this rules?"

    • Yes the HPS EMIF IP also same.


    "So basically the entire cyclone V family do not allow fly-by topology as leveling is not included?"

    • Yes, it's not supporting DDR3 SDRAM fly-by topology


    "DDR3 speed is above 300MHz so do this also applying the same leveling constraints "ON HPS hard EMI"? "

    • Yes


    Regards,

    Adzim


AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
7 months ago

Hi Brian,


"So simply said HPS hard EMI also this rules?"

  • Yes the HPS EMIF IP also same.


"So basically the entire cyclone V family do not allow fly-by topology as leveling is not included?"

  • Yes, it's not supporting DDR3 SDRAM fly-by topology


"DDR3 speed is above 300MHz so do this also applying the same leveling constraints "ON HPS hard EMI"? "

  • Yes


Regards,

Adzim


  • BrianSune_Froum's avatar
    BrianSune_Froum
    Icon for Contributor rankContributor
    6 months ago

    @AdzimZM_Intel

    I am afraid during testing and referencing to Altera inherent design files.

    I am so confused and puzzled why leveling is not allowed but such routing is allowed?

    According to T-Branch layout it is almost defined it must be even # of dies.

    But if the middle join is the ECC it is still understandable but in this route and design it is a fly-by just first node termination.

    This violated all the discussion previously?

    Please do explain.