AdzimZM_Altera
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Re: Agilex 5: LPDDR5 T-line routing for 1CH x 32 configuration
Hi glen-7 , Do you have any reference designs which use the T-line routing style like Figure 32 that I could use as a guide? I think you may refer to the board design from Agilex 5 devkit or Agilex 7 M devkit. Is there any subject matter experts at the factory who might have some advice on this routing topology? You may ask the question and I will try to help on that. Is it possible to use a daisy-chain routing style for the WCK, CK, and CA traces, instead of t-line? Yes it's possible. You may refer to this document for the PCB layout guideline: https://docs.altera.com/r/docs/821801/current/pcb-design-guidelines-hssi-emif-mipi-true-differential-pdn-user-guide-agilextm-5-fpgas-and-socs/lpddr5-interface-design-guidelines Regards, Adzim7Views0likes0CommentsRe: MAX10 DDR3 Timing
Hi Korbinian, Thanks for the update. In this case, can you generate an example design from the DDR3 EMIF IP Editor(from current design) and compile the design? If it an IP setting issue, we might be able see the similar timing in the example design. Regards, Adzim7Views0likes0CommentsRe: QSPI DDR Interface with Cyclone10LP: Maximum frequency
Hi mfbm , "How much does it penalize using 3V3 LVCMOS standard vs. 1,8V in terms of achiveable frequency?" Lower voltage I/O standards (e.g., 1.8V LVCMOS) support higher switching frequencies than higher voltage standards (e.g., 3.3V LVCMOS). This is due to faster rise and fall times and reduced capacitive charging time at lower voltages. Regards, Adzim21Views0likes2CommentsRe: QSPI DDR Interface with Cyclone10LP: Maximum frequency
Hi mfbm, "Does this mean the pins will not be able to accept data changing at a rate faster than 200 MHz or will it be possible to have something like a fHSCLK of 200 MHz (which would mean double device operation in Mbps) as we can see in Table 24 (example for RSDS Transmitter) on the datasheet?" In practice, exceeding 200 MHz with standard I/O (LVCMOS) is generally not supported or reliable due to buffer slew rates, timing constraints, and signal integrity limitations "Are there any special pins on the FPGA which we can use to achieve maximum potential on this interface? Or any strategies like using IDDR/ODDR modules that could help?" Use the fastest I/O standard that your board design supports (e.g., 1.8V LVCMOS for faster edge rates, though still limited to ~200 MHz). Utilize IDDR/ODDR for double data rate operation, but the clock frequency cannot exceed the I/O's rated frequency (200 MHz), and setup/hold timing becomes more challenging at higher rates. Minimize PCB trace lengths, use controlled impedance and proper termination for optimal signal integrity. Synchronize the QSPI clock to the FPGA's internal clock domain to avoid metastability. Consider using parallel I/O banks for a wider data bus if higher throughput is needed. Regards, Adzim14Views0likes4CommentsRe: MAX10 DDR3 Timing
Dear Korbinian, We will continue to monitor this post for the next 5 days. If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions. Thank you for engaging with us! Regards, Adzim13Views0likes0Comments