AdzimZM_Altera
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Re: LPDDR2 External Memory Controller Using Altera Cyclone V GX Dev Kit video is corrupted
Hello MikeZ, I did try to look for the video source but cannot find it. If someone got save the video before then it might help in this case. I find this example project for 4 port LPDDR2 memory interface for the Altera Cyclone 5 GX Starter Kit :https://github.com/csus-senior-design/ram_int_4p/tree/master Please have a look if the example can help you to use the LPDDR2. Regards, Adzim3Views0likes1CommentRe: Unable to simulate DDR3 controller
Hi Juan, FYI, the Intel community will freeze in next 2 weeks for updating the support system for Altera. Meaning you can only read the content but cannot edit or reply in the thread. I also will OOO next week. Thus, I think it's better to close this thread for now. I think your questions have been addressed. I will transition this thread to community support. In next month, you can open a new thread to continue the discussion. Thank you for your understanding. Regards, Adzim302Views0likes0CommentsRe: Intel Arria10 GX Development Kit - DDR3 example design - traffic_gen_fail
Hi ats52, I'm glad that now your issue is resolved. I hope you can continue further to finish your design or project with successful result. I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you. Regards, Adzim218Views0likes0CommentsRe: Intel Arria10 GX Development Kit - DDR3 example design - traffic_gen_fail
Hi ats52, "If I suppose you have an Arria 10 GX Development Kit board, the project I attached works fine on your board?" Currently we have some hardware limitation to test the design. Thus, I cannot test the design you provided. "As far as I've looked into the installer package of arria10GX_10ax115sf45_fpga_v22.4.0_v1.1.zip, it looks only SOF files are included for BTS items, the project designs are not. Is it possible to get the project design for BTS of DDR3? Since BTS and the example design test for DDR3 make difference, I hope I will be able to find some clues if the project is available" You can use the design from "arria10GX_10ax115sf45_fpga_v22.4.0_v1.1.zip\arria10GX_10ax115sf45_fpga_v22.4.0_v1.1\examples\memory\PRD\qts_ddr3_x72_1066MHz" to run the test. I think it's similar to BTS design. Regards, Adzim417Views0likes1CommentRe: Unable to simulate DDR3 controller
Hi Juan, You can add the e0 instance in the Wave windows before run the simulation if you like to see the avalon interface and other signal. You should be running correct simulation at this point. The simulation doesn't have hardware, thus it's create a module to represent the hardware in order to simulate the signal, IP, etc. Therefore, the instances in simulation may a bit different from the Quartus design. You need to check the instance for the object that you need to simulate. I'm not sure if there is any instruction to migrate the design. I think we don't provide that. You need to manually add the files into your design. Regards, Adzim420Views0likes0CommentsRe: Intel Arria10 GX Development Kit - DDR3 example design - traffic_gen_fail
Hi ats52, Are you using the bts design with version v15.1.2? (arria10GX_10ax115sf45_fpga_v15.1.2) If yes, the row address width is set to 16 and RZQ pin is assigned in Bank 2J in this design. I will share the example design later. Please test the design and check for the status (LED). Regards, Adzim488Views0likes1Comment