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AdzimZM_Altera
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Re: 10AX115N3F40E2SG DDR test fail
Hi Luke_J1986 , I don't think there is any silicon changes other than IP fixes during that time. You may try below suggestion to identify the problem: Confirm identical .sof/.pof and Quartus version were used before/after swap. Check whether the failure is at DDR calibration/training or later memory traffic. Compare supply rails during DDR init: core, VCCIO, VREF, VTT. Inspect BGA rework quality on the FPGA and nearby DDR components. Try the 2023 part on the other 2 known-good PCBAs to see whether the failure follows the chip or stays with the board. If possible, reduce DDR speed or relax margin to see whether it becomes stable. Regards, Adzim22Views1like0CommentsRe: SDRAM ( Single Data Rate ) refresh verilog
Hi DarkSideOfTheSignal Looks like you have managed to slowly resolve the issue. I'm not sure how I can help you on this issue but I think you can also try a simulation run based on SDRAM IP design and observe the waveform. Maybe you can get more idea based on that.14Views0likes1CommentRe: User controlled burst refresh
Hi Masaru, When user control refresh is enabled, user has complete control and responsible to provide sufficient refresh to memory. The statement in EMIF UG mentioned it here: https://docs.altera.com/r/docs/683663/24.1/external-memory-interfaces-cyclone-10-gx-fpga-ip-user-guide/intel-cyclone-10-gx-emif-ip-ddr3-parameters-controller The IP should enable the user control refresh already. I don't think you need to enable it from the user logic. Regards, Adzim14Views0likes3CommentsRe: Minimum pulse width violation on EMIF-HPS
Hi annamalairaj, Can you also share the hps subsystem qsys file? I tried to replicate the issue. So far do not able to see the timing violation within the HPS EMIF clock and HPS. Can you try use one of the performance option from the compiler settings? In Quartus goto: Assignments -> Settings -> Compiler Settings. You may refer to EMIF document to optimize timing here:https://docs.altera.com/r/docs/683216/23.2/external-memory-interfaces-agilextm-7-f-series-and-i-series-fpga-ip-user-guide/optimizing-timing Regards, Adzim18Views0likes0Comments