AdzimZM_Altera
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Re: SDRAM ( Single Data Rate ) refresh verilog
Hi DarkSideOfTheSignal Looks like you have managed to slowly resolve the issue. I'm not sure how I can help you on this issue but I think you can also try a simulation run based on SDRAM IP design and observe the waveform. Maybe you can get more idea based on that.10Views0likes1CommentRe: User controlled burst refresh
Hi Masaru, When user control refresh is enabled, user has complete control and responsible to provide sufficient refresh to memory. The statement in EMIF UG mentioned it here: https://docs.altera.com/r/docs/683663/24.1/external-memory-interfaces-cyclone-10-gx-fpga-ip-user-guide/intel-cyclone-10-gx-emif-ip-ddr3-parameters-controller The IP should enable the user control refresh already. I don't think you need to enable it from the user logic. Regards, Adzim3Views0likes3CommentsRe: Minimum pulse width violation on EMIF-HPS
Hi annamalairaj, Can you also share the hps subsystem qsys file? I tried to replicate the issue. So far do not able to see the timing violation within the HPS EMIF clock and HPS. Can you try use one of the performance option from the compiler settings? In Quartus goto: Assignments -> Settings -> Compiler Settings. You may refer to EMIF document to optimize timing here:https://docs.altera.com/r/docs/683216/23.2/external-memory-interfaces-agilextm-7-f-series-and-i-series-fpga-ip-user-guide/optimizing-timing Regards, Adzim14Views0likes0CommentsRe: User controlled burst refresh
Hi Masaru, 1. "Should I clear the mmr_refresh_req register before back-to-back next refresh request?" - No the IP should handle it. 2. "What happens if I disable the auto-precharge control? In this case, are both IP planned refresh and user controlled refresh happens?" - You should control the refresh since the IP doesn't issue the refresh if user controlled refresh is enabled. 3. "What is the relationship of them? Does the IP parameter define initial state of cfg_user_rfsh_en register? Is the logical AND condition needed for the user controlled refresh?" - You don't have to care about that. Only use the MMR interface. 4. "Do I need to handle this register?" - No need. Regards, Adzim2Views0likes5Comments