AdzimZM_AlteraRegular ContributorJoined 4 years ago1085 Posts33 LikesLikes received82 SolutionsView All Badges
ContributionsMost RecentMost LikesSolutionsRe: Multi Port front end IP for the single port DDR4 memory controller - Stratix10 TX Please let me know if you have further question on this thread. Re: Agilex 7 HBM2E burst length Hi FBuss2 , HBM2E operates with fixed internal burst lengths (BL4/BL8). In BL8 mode, each internal column access returns a full BL8 worth of data. A 1‑beat AXI write on a narrow port often forces read‑modify‑write internally; a 1‑beat read fetches a full internal BL8 but delivers only one byte on AXI. This is highly inefficient and can degrade throughput and increase power. Regards, Adzim Re: Agilex 7 HBM2E burst length Hi FBuss2, AXSIZE = 110 is a 64 bytes transfer but the HBM setting is used only 256 bit. Maybe you can use AXSIZE = 101 for 32 bytes transfer. I think the burst length = 1 can still run the test but our recommendation is to use burst length at least 2 if BL8 or fabric NOC is enabled. Regards, Adzim Re: Agilex5 / IBIS HSIO - LPDDR4 Hi ohfpga1, Do you have any further question? Regards, Adzim Re: Error : Arria 10 emif_reset_ interrupt acknowledge Hi SUHAS_KRISHNA, Any feedback in this forum? Regards, Adzim Re: Multi Port front end IP for the single port DDR4 memory controller - Stratix10 TX Hi amol, We don't provide the MPFE IP core for Stratix 10 devices. You may create a MPFE-like design using the bridge and interconnect logic in Platform Designer. For example, if multiple FPGA modules need to access the same EMIF IP , you need an EMIF IP and multiple Avalon Memory Mapped Pipeline Bridges in Platform Designer. The bridges can be connected to the EMIF IP through a master. The interconnect logic will be handle by Platform Designer. The FPGA modules then can connect to slave of the bridges. Regards, Adzim Re: AXC3000 Agilex 3 board Hi Iw1esu Let me know if further assistance is needed from my side. Regards, Adzim Re: Agilex 7 HBM2E burst length Hi FBuss2, When running the test, what is the AXSIZE and AXLEN you used? Could be possible the test has cross 4KB boundary. Regards, Adzim Re: Agilex 7 HBM2E burst length Hi FBuss2, Sorry for the delay to reply. I was OOO last week and not able to reply on time. Can you provide the HBM2E IP setting that you configured? Are you testing on a Agilex 7 M devkit or a custom board? Did you used example design to run the test or used your own design? Regards, Adzim Re: Agilex5 / IBIS HSIO - LPDDR4 Hi ohfpga1, "which are IBIS models to use among that list ? We are supposing « lvstl11_io_s3r40c_doff » and « dlvstl11_io_s3r40c_doff »." Yes that model should be okay. There should be a document that explain the IBIS model and nomenclature which may help you to identify the model. Regards, Adzim