AdzimZM_Altera
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Re: Agilex 7 DDR4 Reset and ADDR/CMD Clock PCB Implementation Documentation Discrepancy
Hi Steve9 , "Can Altera explain why they recommend pullup which seems to be opposite of what memory vendor specifies?" The power need to apply to reset_n pin at power-up sequence as mention in datasheet. "why the eval board implementation for this signal termination does not match the EMIF user guide figure 143 recommendation?" There are multiple termination scheme that has been used to terminate the clk signal. You can also terminate the signal to VDD. Also can terminate to both VDD and GND. I think the board designer should identify which termination scheme that suitable for their board. Regards, Adzim2Views0likes0CommentsRe: Timing Slacks inside Altera IP
Hi Omer1, Please help to provide more information to help on clarify the issue. I guess the a10_internal_oscillator_clock0 is a reference clock to EMIF IP. Correct me if I'm wrong. Any other instance that used same clock for the clock source in your design? Is there any other instances that has been connected to EMIF IP? Can you try to remove other IP and fit the EMIF IP first in the design? Then observe if the timing violation is still there. Regards, Adzim13Views0likes1CommentRe: MAX10 DDR3 Timing
Hi Korbinian, For those nsleep error, you need to make sure that the device is 10M16DAF484I6G or support device with DDR3. Try to add this timing contraint into your sdc file because the reset synchroinzer may cause timing violation set_false_path -from altera_reset_controller:rst_controller*|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out -to *:if0|*:p0|*_memphy_m10:umemphy|*_reset_m10:ureset|*_reset_sync:*|reset_reg[*] And also set the Compiler setting to Performance: And Optimization Technique to Speed in Advanced Settings (Synthesis):9Views0likes0CommentsRe: Agilex 5: LPDDR5 T-line routing for 1CH x 32 configuration
Hi glen-7 , Do you have any reference designs which use the T-line routing style like Figure 32 that I could use as a guide? I think you may refer to the board design from Agilex 5 devkit or Agilex 7 M devkit. Is there any subject matter experts at the factory who might have some advice on this routing topology? You may ask the question and I will try to help on that. Is it possible to use a daisy-chain routing style for the WCK, CK, and CA traces, instead of t-line? Yes it's possible. You may refer to this document for the PCB layout guideline: https://docs.altera.com/r/docs/821801/current/pcb-design-guidelines-hssi-emif-mipi-true-differential-pdn-user-guide-agilextm-5-fpgas-and-socs/lpddr5-interface-design-guidelines Regards, Adzim14Views0likes0CommentsRe: MAX10 DDR3 Timing
Hi Korbinian, Thanks for the update. In this case, can you generate an example design from the DDR3 EMIF IP Editor(from current design) and compile the design? If it an IP setting issue, we might be able see the similar timing in the example design. Regards, Adzim16Views0likes0Comments