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AdzimZM_Altera
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Re: HyperRAM Hyperbus options for Agilex
Hi glenenglish , The LPDDR4 16 bit design can be fit in 1 sub bank. The other sub bank can be used with difference VCCIO_PIO because each sub bank has it's own VCCIO_PIO power supply. You can refer to GPIO UG: https://docs.altera.com/r/docs/813934/25.3.1/general-purpose-i/o-user-guide-agilextm-5-fpgas-and-socs/supported-i/o-standards-for-hsio-banks I've provided a design that shows LPDDR4 design can fit in 1 sub bank and the other sub bank is using 1.2V VCCIO.41Views0likes0CommentsRe: Agilex 5 FPGA EMIF: sharing LPDDR4 reference clock between Bank 3A and Bank 3B
Hi Gonza , For the FPGA LPDDR4 External Memory Interfaces (EMIF) IP, is it mandatory that the PLL reference clock be located in the same bank as the EMIF instance? We recommended to have the refclk placed within the Address and Command Group of each interface. While sharing PLL reference clock within an IO Bank is still permitted. Is there any supported mechanism to share or bypass the PLL reference clock from the EMIF PLL in bank 3A to the EMIF PLL in bank 3B, similar to what appears to be done automatically by the HPS EMIF 2x32 implementation? You can use clock bridge IP to supply the clock to both EMIF interfaces across the banks. If you still facing the issue, please share the example design for debugging purpose. Regards, Adzim48Views0likes1CommentRe: 10AX115N3F40E2SG DDR test fail
Hi Luke_J1986 , I don't think there is any silicon changes other than IP fixes during that time. You may try below suggestion to identify the problem: Confirm identical .sof/.pof and Quartus version were used before/after swap. Check whether the failure is at DDR calibration/training or later memory traffic. Compare supply rails during DDR init: core, VCCIO, VREF, VTT. Inspect BGA rework quality on the FPGA and nearby DDR components. Try the 2023 part on the other 2 known-good PCBAs to see whether the failure follows the chip or stays with the board. If possible, reduce DDR speed or relax margin to see whether it becomes stable. Regards, Adzim38Views1like0CommentsRe: SDRAM ( Single Data Rate ) refresh verilog
Hi DarkSideOfTheSignal Looks like you have managed to slowly resolve the issue. I'm not sure how I can help you on this issue but I think you can also try a simulation run based on SDRAM IP design and observe the waveform. Maybe you can get more idea based on that.19Views0likes1CommentRe: User controlled burst refresh
Hi Masaru, When user control refresh is enabled, user has complete control and responsible to provide sufficient refresh to memory. The statement in EMIF UG mentioned it here: https://docs.altera.com/r/docs/683663/24.1/external-memory-interfaces-cyclone-10-gx-fpga-ip-user-guide/intel-cyclone-10-gx-emif-ip-ddr3-parameters-controller The IP should enable the user control refresh already. I don't think you need to enable it from the user logic. Regards, Adzim20Views0likes3CommentsRe: Minimum pulse width violation on EMIF-HPS
Hi annamalairaj, Can you also share the hps subsystem qsys file? I tried to replicate the issue. So far do not able to see the timing violation within the HPS EMIF clock and HPS. Can you try use one of the performance option from the compiler settings? In Quartus goto: Assignments -> Settings -> Compiler Settings. You may refer to EMIF document to optimize timing here:https://docs.altera.com/r/docs/683216/23.2/external-memory-interfaces-agilextm-7-f-series-and-i-series-fpga-ip-user-guide/optimizing-timing Regards, Adzim27Views0likes0Comments