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BrianSune_Froum's avatar
BrianSune_Froum
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1 year ago
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Custom board on Cyclone V SoC HPS SDRAM topology unclear

Dear Intel and All, This is Brian, I am working on a C5 SoC project. According to document "emi_plan-683385-666390.pdf" "Leveling circuitry is dedicated I/O circuitry to provide calibration supp...
Board Debug
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    1 year ago

    Hi Brian,


    "So simply said HPS hard EMI also this rules?"

    • Yes the HPS EMIF IP also same.


    "So basically the entire cyclone V family do not allow fly-by topology as leveling is not included?"

    • Yes, it's not supporting DDR3 SDRAM fly-by topology


    "DDR3 speed is above 300MHz so do this also applying the same leveling constraints "ON HPS hard EMI"? "

    • Yes


    Regards,

    Adzim


BrianSune_Froum's avatar
BrianSune_Froum
Icon for Contributor rankContributor
1 year ago

The final result is that even with a fly-by routed topology there are no issue on both 1.5V and 1.35V DDR3 DDR3L.
The MT41K128M16 /w 1k page size shows no sanity issue on memtest stresapptest on distro.
UBOOT memory normal test also passed w/o any errors.

So after short testing we can only assume there are inherent bug on Quartus 18.1? or HPS IP.

No matter it is /w or /wo the board settings no drop no crash no stuck.

So the case ends here.