Forum Discussion
ContributorCustom board on Cyclone V SoC HPS SDRAM topology unclear
Hi Brian,
"So simply said HPS hard EMI also this rules?"
- Yes the HPS EMIF IP also same.
"So basically the entire cyclone V family do not allow fly-by topology as leveling is not included?"
- Yes, it's not supporting DDR3 SDRAM fly-by topology
"DDR3 speed is above 300MHz so do this also applying the same leveling constraints "ON HPS hard EMI"? "
- Yes
Regards,
Adzim
Regular ContributorHi Brian,
"So simply said HPS hard EMI also this rules?"
- Yes the HPS EMIF IP also same.
"So basically the entire cyclone V family do not allow fly-by topology as leveling is not included?"
- Yes, it's not supporting DDR3 SDRAM fly-by topology
"DDR3 speed is above 300MHz so do this also applying the same leveling constraints "ON HPS hard EMI"? "
- Yes
Regards,
Adzim
ContributorI am afraid during testing and referencing to Altera inherent design files.
I am so confused and puzzled why leveling is not allowed but such routing is allowed?
According to T-Branch layout it is almost defined it must be even # of dies.
But if the middle join is the ECC it is still understandable but in this route and design it is a fly-by just first node termination.
This violated all the discussion previously?
Please do explain.
