Forum Discussion
ContributorCustom board on Cyclone V SoC HPS SDRAM topology unclear
Hi Brian,
"So simply said HPS hard EMI also this rules?"
- Yes the HPS EMIF IP also same.
"So basically the entire cyclone V family do not allow fly-by topology as leveling is not included?"
- Yes, it's not supporting DDR3 SDRAM fly-by topology
"DDR3 speed is above 300MHz so do this also applying the same leveling constraints "ON HPS hard EMI"? "
- Yes
Regards,
Adzim
Super ContributorIt's been a while since I've used DDR3, but fly-by is certainly allowed. You specify in the IP Parameter Editor that the memory is organized in such a topology and that enables the automatic leveling based on when signals reach each chip. It's recommended for most implementations but required at 400 MHz and above.
BrianSune_FroumMaybe allow me to rephase or explain a bit more what i am trying to ask or confirm.
What i am seeking is a confirmation on HPS hard memory controller that is allow user to design in fly-by topology.
I am not asking about the external memory controller in PL side.
If this is align with what you had mentioned please do confirm or provide documents I am willing to read more.Thank you
- sstrell
TBH, it's not clear: https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/sdram-controller-subsystem-40997.html
I know the hard memory controller in the CV fabric does support fly-by. It is not mentioned in this HPS documentation.
The easiest thing to do would be to simply create an HPS instance in Platform Designer and see if the option is there in the component's parameter editor.
- BrianSune_Froum
I am afraid there are still no information to confirm such.
Meanwhile, there are still more puzzling factors.
If possible do you have any idea that Altera do have open example layout from the beginning for engineer to reference?
Appreciated
