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ContributorCustom board on Cyclone V SoC HPS SDRAM topology unclear
Hi Brian,
"So simply said HPS hard EMI also this rules?"
- Yes the HPS EMIF IP also same.
"So basically the entire cyclone V family do not allow fly-by topology as leveling is not included?"
- Yes, it's not supporting DDR3 SDRAM fly-by topology
"DDR3 speed is above 300MHz so do this also applying the same leveling constraints "ON HPS hard EMI"? "
- Yes
Regards,
Adzim
Regular ContributorHi Brian,
Leveling is not supported for Cyclone V device.
Please refer to this link in Note 10: https://www.intel.com/content/www/us/en/docs/programmable/683841/17-0/uniphy-based-external-memory-interface.html
For reference material, you may refer to to Cyclone V SoC devkit.
https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/cyclone/v-sx.html
Regards,
Adzim
BrianSune_Froum
Please do confirm the below understanding is aligned." 13. For Arria V, Arria V GZ, Cyclone V, and Stratix V."
So simply said HPS hard EMI also this rules?
" 10. & 13."
So basically the entire cyclone V family do not allow fly-by topology as leveling is not included?
"10. Leveling is not available for Arria V or Cyclone V devices."
DDR3 speed is above 300MHz so do this also applying the same leveling constraints "ON HPS hard EMI"?
Thank you
