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BrianSune_Froum's avatar
BrianSune_Froum
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7 months ago
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Custom board on Cyclone V SoC HPS SDRAM topology unclear

Dear Intel and All, This is Brian, I am working on a C5 SoC project. According to document "emi_plan-683385-666390.pdf" "Leveling circuitry is dedicated I/O circuitry to provide calibration supp...
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  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    7 months ago

    Hi Brian,


    "So simply said HPS hard EMI also this rules?"

    • Yes the HPS EMIF IP also same.


    "So basically the entire cyclone V family do not allow fly-by topology as leveling is not included?"

    • Yes, it's not supporting DDR3 SDRAM fly-by topology


    "DDR3 speed is above 300MHz so do this also applying the same leveling constraints "ON HPS hard EMI"? "

    • Yes


    Regards,

    Adzim


BrianSune_Froum's avatar
BrianSune_Froum
Icon for Contributor rankContributor
7 months ago

@AdzimZM_Intel


Please do confirm the below understanding is aligned.

" 13. For Arria V, Arria V GZ, Cyclone V, and Stratix V."

So simply said HPS hard EMI also this rules?


" 10. & 13."
So basically the entire cyclone V family do not allow fly-by topology as leveling is not included?

"10. Leveling is not available for Arria V or Cyclone V devices."
DDR3 speed is above 300MHz so do this also applying the same leveling constraints "ON HPS hard EMI"?

Thank you