Honored ContributorI want to design a combinatorial circuit for an fpga which will count the position of ones in a 16 bit vector.
eg1 if vector is 16'b0000_0000_0011_0101 then output should be 64'h0000_0000_0000_5420 eg2 if vector is 16'b0000_1010_0000_1010 then output should be 64'h0000_0000_0000_b931. Please help. Thanks in advance....
Honored ContributorHonored ContributorHonored ContributorIt is sad that in many fora across the web simple solutions get drowned in garbage.
The for loop unfolds to comb logic as follows: if input(0) = '1' then .... end if; if input(1) = '1' then .... end if; if input(2) = '1' then .... end if; etc. until input(15) The compiler unrolls it at compile time. It is just for convenience of writing multiple statements.Honored ContributorHonored ContributorI found, that the pure combinational solution (without the registers implemented by josyb) results in a tpd of about 17 ns with Cyclone III. So 266 MHz would surely need pipelining.
I didn't try, if the synthesis tool will "pull-in" registers to the synthesis of the behavioral description. As previously reported in the Forum, it does e.g. in the case of a parallel divider. But most likely, you have to break the data path manually to achieve the speed requirement.Honored ContributorWow, a lot of activity while I was away ...
I only added the input and output registers to measure the speed (in TimeQuest you don't get tPD reports unless you set constraints and I was doing this test in QII 10.1SP1) and second to give the compiler a fair chance to get a high speed. Double registering the outputs may even help a bit more. While driving home from the office last night I mused that I could have written it as a function giving a better view:
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bitpos is
generic (
WIDTH_D : positive := 16
) ;
port (
Clk : in std_logic ;
data_in : in std_logic_vector(WIDTH_D - 1 downto 0) ;
data_out : out std_logic_vector(WIDTH_D * 4 - 1 downto 0)
);
end bitpos ;
architecture a of bitpos is
function reportbitpos( v : std_logic_vector)
return std_logic_vector
is
variable j : natural ;
variable r : std_logic_vector(v'length * 4 - 1 downto 0) ;
begin
j := 0 ;
r := (others => '0') ;
for i in 0 to v'high loop
if v(i) = '1' then
r(j*4+3 downto j*4) := std_logic_vector(to_unsigned(i,4));
j := j + 1 ;
end if;
end loop;
return r ;
end function ;
signal ld : std_logic_vector(WIDTH_D - 1 downto 0) ;
begin
process(clk)
begin
if rising_edge(Clk ) then
ld <= data_in ;
data_out <= reportbitpos( ld ) ;
end if ;
end process;
end a ;It looks like Altera 'progresses' on VHDL support on each subsequent release. E.g. 9.1SP2 supports VHDL 2008 but only a subset, 10.1 supports a bit more, but not yet everything (not that we need everything ...). Maybe this also the case with VHDL-1993 support.
Honored ContributorHonored Contributor
