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22 Replies
- Altera_Forum
Honored Contributor
no bugs, no hassle of spaghetti
additionally you can add clock or change indexinglibrary ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity test is port( din : in std_logic_vector(0 to 15); dout: out std_logic_vector(0 to 63) ); end entity; architecture a of test is begin process(din) begin for i in 0 to 15 loop if din(i) = '0' then dout(i*4 to i*4+3) <= "0000"; else dout(i*4 to i*4+3) <= std_logic_vector(to_unsigned(i,4)); end if; end loop; end process; end a; - Altera_Forum
Honored Contributor
--- Quote Start --- no bugs, no hassle of spaghetti --- Quote End --- This solution is of course consuming much less logic resources, but not corresponding to the original specification - whatever may be it's purpose.