Forum Discussion
Altera_Forum
Honored Contributor
14 years ago --- Quote Start --- This is a "bug" thats been around a while, and have mentioned on our internal wiki. --- Quote End --- Thanks for clarifying. According to josyb, it has been already fixed in V9.1SP2. I accepted the limitation when working with previous Quartus versions and didn't yet figure out, if a variable slice range is required by the VHDL standard. Do you know the exact paragraph in IEEE 1076?