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Altera_Forum
Honored Contributor
14 years ago --- Quote Start --- I used the VHDL 1993 setting in QII 9.1SP2 that I use for waveform simulation. Actually 9.1SP2 produces a faster circuit then 10.1SP1. --- Quote End --- I didn't yet proceed to Quartus 10. I compiled under V9.0 with VHDL 1993 settings and got the below error with your recent code. I was under the assumption, that constant slice ranges are required, no idea which other setting may be different. But the point isn't very important. --- Quote Start --- Error (10394): VHDL error at bitpos.vhd(29): left bound of range must be a constant --- Quote End ---