Forum Discussion
Altera_Forum
Honored Contributor
14 years ago --- Quote Start --- I didn't yet proceed to Quartus 10. I compiled under V9.0 with VHDL 1993 settings and got the below error with your recent code. I was under the assumption, that constant slice ranges are required, no idea which other setting may be different. But the point isn't very important. --- Quote End --- This is a "bug" thats been around a while, and have mentioned on our internal wiki. Apparently only Quartus has had a problem with it, no concerns with ISE or Modelsim. Maybe they finally fixed it with Q10!