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Actually it can be done in a combinatorial way but you dont take a case statement approach... i think there is a way...
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Case statements would only inflate the code. josyb has shown an exact solution of your original problem, taking advantage of the VHDL iteration constructs. If you want a pure combinational solution for some reason, you can simply remove the
if rising_edge(clk) condition.
The assignment to the slice
lq(j*4+3 downto j*4) isn't accepted at least by my VHDL version, I think a slice must generally needs a constant range. I used a bitwise copy instead.
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i dont know how to remove those extra zeros.
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The suggested solution gives the results specified in your original post.
Honored Contributor
