Counting the position of ones in a binary vector

Wow, a lot of activity while I was away ...

I only added the input and output registers to measure the speed (in TimeQuest you don't get tPD reports unless you set constraints and I was doing this test in QII 10.1SP1) and second to give the compiler a fair chance to get a high speed. Double registering the outputs may even help a bit more.

While driving home from the office last night I mused that I could have written it as a function giving a better view:

library ieee;
	use ieee.std_logic_1164.all;
	use IEEE.numeric_std.all;
	
	
	
entity bitpos is
	generic (
		WIDTH_D : positive := 16 
		) ;
	port (
		Clk		:	in	std_logic ;
		data_in		:	in	std_logic_vector(WIDTH_D - 1 downto 0) ;
		data_out	:	out	std_logic_vector(WIDTH_D * 4 - 1 downto 0) 
		);
	end bitpos ;
		
architecture a of bitpos is
	function reportbitpos( v : std_logic_vector)
		return std_logic_vector 
		is
			variable j : natural ;
			variable r : std_logic_vector(v'length * 4 - 1 downto 0) ;
		begin
			j := 0 ;
			r := (others => '0') ;
			for i in 0 to v'high loop
				if v(i) = '1' then
				r(j*4+3 downto j*4) := std_logic_vector(to_unsigned(i,4));
				j := j + 1 ;
				end if;
			end loop;
			return r ;
		end function  ;
	signal	ld	:	std_logic_vector(WIDTH_D - 1 downto 0) ;
begin
	process(clk)
	begin
		if rising_edge(Clk ) then
			ld <= data_in ;
			data_out <= reportbitpos( ld ) ;
		end if ;
	end process;
end a ;

At the same time I added the generic to find out when we cross the 266 MHz border, at width 8 we get about 200 MHz, at width 4 500MHz+ or maximum speed.

A fully pipelined design will need about 1280 registers, and run at maximum speed.

Using a Cyclone IV E in stead of a Cyclone II ups the speed form 110 to 121 MHz for a 16 bit input vector (with a tCK setting of 8.0 ns) Compiling it for a width of 8 it gets up to 237 MHz.

to FvM:

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The assignment to the slice lq(j*4+3 downto j*4) isn't accepted at least by my VHDL version, I think a slice must generally needs a constant range. I used a bitwise copy instead.

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I used the VHDL 1993 setting in QII 9.1SP2 that I use for waveform simulation. Actually 9.1SP2 produces a faster circuit then 10.1SP1.