Honored ContributorI want to design a combinatorial circuit for an fpga which will count the position of ones in a 16 bit vector.
eg1 if vector is 16'b0000_0000_0011_0101 then output should be 64'h0000_0000_0000_5420 eg2 if vector is 16'b0000_1010_0000_1010 then output should be 64'h0000_0000_0000_b931. Please help. Thanks in advance....
Honored ContributorThis will not be straightforward to realise in a combinatorial circuit because what you describe is a rather sequential process: traverse the input vector from right to left, if you encounter a bit set to '1' add its position index into the next available output slot.
This doesn't mean it can't be done combinatorially, but the result will be huge as it has to cater for all combinations (all 65356 of them ...).Honored Contributoronly as guide, not tested
process(data_in)
begin
for i in 0 to 15 loop
if data_in(i) = '0' then
data_out(i*4:i*4+3) <= "0000";
else
data_out(i*4:i*4+3) <= std_logic_vector(to_unsigned(i,4));
end if;
end loop;
end process;
process(data_in)
begin
for i in 0 to 15 loop
if data_in(i) = '0' then
data_out(i*4:i*4+3) <= "0000";
else
data_out(i*4:i*4+3) <= std_logic_vector(to_unsigned(i,4));
end if;
end loop;
end process;
process(data_in)
variable j : natural ;
begin
j := 0 ;
data_out <= (others => '0') ;
for i in 0 to 15 loop
if data_in(i) = '1' then
data_out(j*4:j*4+3) <= std_logic_vector(to_unsigned(i,4));
j := j + 1 ;
end if;
end loop;
end process;the loop index is going up anyway. for bit index 3 then output nibble = 3 if it is '1' else nibble = 0
Honored ContributorHonored ContributorAnd simulated. 466 LC, 80 registers, 105 MHz in a Cyclone II EP2C5F256C6.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bitpos is
port (
Clk : in std_logic ;
data_in : in std_logic_vector(15 downto 0) ;
data_out : out std_logic_vector(63 downto 0)
);
end bitpos ;
architecture a of bitpos is
signal ld : std_logic_vector(15 downto 0) ;
begin
process(clk)
variable j : natural ;
variable lq : std_logic_vector(63 downto 0) ;
begin
if rising_edge(Clk ) then
ld <= data_in ;
j := 0 ;
lq := (others => '0') ;
for i in 0 to 15 loop
if ld(i) = '1' then
lq(j*4+3 downto j*4) := std_logic_vector(to_unsigned(i,4));
j := j + 1 ;
end if;
end loop;
data_out <= lq ;
end if ;
end process;
end a ;
process(data_in)
begin
for i in 0 to 15 loop
if data_in(i) = '0' then
data_out(i*4:i*4+3) <= "0000";
else
data_out(i*4:i*4+3) <= std_logic_vector(to_unsigned(i,4));
end if;
end loop;
end process;
Thanks for your replies..people.
