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Honored Contributor
14 years agoAnd simulated. 466 LC, 80 registers, 105 MHz in a Cyclone II EP2C5F256C6.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bitpos is
port (
Clk : in std_logic ;
data_in : in std_logic_vector(15 downto 0) ;
data_out : out std_logic_vector(63 downto 0)
);
end bitpos ;
architecture a of bitpos is
signal ld : std_logic_vector(15 downto 0) ;
begin
process(clk)
variable j : natural ;
variable lq : std_logic_vector(63 downto 0) ;
begin
if rising_edge(Clk ) then
ld <= data_in ;
j := 0 ;
lq := (others => '0') ;
for i in 0 to 15 loop
if ld(i) = '1' then
lq(j*4+3 downto j*4) := std_logic_vector(to_unsigned(i,4));
j := j + 1 ;
end if;
end loop;
data_out <= lq ;
end if ;
end process;
end a ; It uses a lot less resources than I initially guessed. Just showing how awesome powerful VHDL is. (Verilog very, very probably too)