Forum Discussion
Altera_Forum
Honored Contributor
14 years ago --- Quote Start --- only as guide, not tested
process(data_in)
begin
for i in 0 to 15 loop
if data_in(i) = '0' then
data_out(i*4:i*4+3) <= "0000";
else
data_out(i*4:i*4+3) <= std_logic_vector(to_unsigned(i,4));
end if;
end loop;
end process;
--- Quote End --- That doesn't do what ganeshmirajkar put forward, as e.g. bitposition 3 will always fill something into output nibble 3. So we need at least a variable. Steeling your code snippet: process(data_in)
variable j : natural ;
begin
j := 0 ;
data_out <= (others => '0') ;
for i in 0 to 15 loop
if data_in(i) = '1' then
data_out(j*4:j*4+3) <= std_logic_vector(to_unsigned(i,4));
j := j + 1 ;
end if;
end loop;
end process; I wonder how this compiles.