Asynchronous adress decoder

Hello,

According to your description of the component behaviour it seems that there is a wait for a read access. Look at the join picture. If I understand well, your component has the same behaviour than the first picture, which has a wait parameter of 1. The second has no wait and the read data is provided on the same clock cycle than the request.

If I misunderstood the behaviour of your component, sorry.

Trick : you can write "00000000" & counter instead of what you wrote. You can even write X"00" & counter (X is to tell that the value is given in hexadecimal base)

Jérôme

Combinational logic, as described above, is fully synthesizable. If it's also reasonable depends on the design purpose, which is unknown so far.

Your VHDL version is not exactly matching the AHDL code, I think. The latter is not writing zero to unsunused output bits or to all output bits in an "others" case. However, when not setting q in all cases, Quartus will warn about latch inference for q, which may be either intended or not, depending on the exact functional definition.

P.S.: You didn't show the full AHDL code. Has the output signal an explicite or implicite default value of zero?

Hi guys,

thanks for your replies!

@Jérôme: The AHDL design used to have the behaviour with NO wait states (like the diagram below in your attachment). The "Interface to User Logic" component in my heired SOPC design confirmed this because it uses a waitstate of '0'

In the first step of my porting to VHDL I made the mistake that I put the case-statement into the clock sensitive process. Therefore I had no chance to communicate with the SOPC system without any waitstates because I first had to register the adress on the first clock cycle after the master had set the adress on the avalon bus. At that time the avalon module was already reading the data which leads to an error.

After I found that out I tried to impelement the adress decoding like in the AHDL modul which seems to be combinatorical instead of synchronous.

The result was that I made an adress sensitive process in my VHDL module which (hopefully) behaves like the AHDL model.

@thepancake: That sounds interesting. Can you please specify how you can simulate a AHDL design in modelsim? As far as I knew, modelsim is only capable of Verilog or VHDL.

@FvM: I was aware about the fact that combinatorical logic is synthesizable. But I'm not quiet sure if it is reasonable to use this in an adress decoder logic. Well in my case I don't have an other chance if I would like to port the AHDL design to VHDL because as I described above the SOPV system uses no wait states. As this is an heired project, I ask myself if this sort of design is safe or if it has some hidden traps. If I say safe I mean is it common practice to implement adress decoders in combinatorical logic or is there a recommendation to implement it in synchronous logic? If so, then I have to change the SOPC module in the way to use at least 1 wait state.

I don't understand your question about the implicite or explicite default value of the AHDL code. Could you please explain?

Thanks,

Maik

Well, below the line, you are right . . .

If you say that Quartus is building the same combinatorical logic for both designs then it should work because it worked in AHDL as expected (or better to say: with no recognizable sideeffects . . ). I was not quiet sure if it is the case that the synthezized logic is the same. At least, if I look into the RTL of both designs they look different.

But maybe here is a very experienced user who says: "Well, you can do it this way but I would recommend to do it in an other way because . . . "

Personally I wonder why it is designed in such an asynchronous way because I would prefer the synchronous way. On the other side I'm a little fearfull to change this because if I get additional wait states and maybe my whole project gets timing issues I don't understand. . .

Maik

@thepancake: Thanks for this hint. Maybe this will save a lot of time for me in the future.

Maik