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Altera_Forum
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16 years ago

Asynchronous adress decoder

Hi, I have heired an old design which contains of a lot of AHDL moduls. I would like to rewrite these moduls into VHDL so that I can simulate them in modelsim. One thing I realized is that...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hello,

According to your description of the component behaviour it seems that there is a wait for a read access. Look at the join picture. If I understand well, your component has the same behaviour than the first picture, which has a wait parameter of 1. The second has no wait and the read data is provided on the same clock cycle than the request.

If I misunderstood the behaviour of your component, sorry.

Trick : you can write "00000000" & counter instead of what you wrote. You can even write X"00" & counter (X is to tell that the value is given in hexadecimal base)

Jérôme