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Honored Contributor
Honored ContributorAsynchronous adress decoder
Hi, I have heired an old design which contains of a lot of AHDL moduls. I would like to rewrite these moduls into VHDL so that I can simulate them in modelsim. One thing I realized is that...
Altera_ForumHonored Contributor
Honored Contributorcheck out Generating Post-Synthesis Simulation Netlist Files in http://www.altera.com/literature/hb/qts/qts_qii53025.pdf on page 9. it won't give you the same flexibility of looking at internal signals like an RTL simulation, but you can make an AHDL file the top level of your project, export a VHDL netlist (called a .vho), and compile/simulate that in ModelSim.
