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Honored Contributor
Honored ContributorAsynchronous adress decoder
Hi, I have heired an old design which contains of a lot of AHDL moduls. I would like to rewrite these moduls into VHDL so that I can simulate them in modelsim. One thing I realized is that...
Altera_ForumHonored Contributor
Honored ContributorWell, below the line, you are right . . .
If you say that Quartus is building the same combinatorical logic for both designs then it should work because it worked in AHDL as expected (or better to say: with no recognizable sideeffects . . ). I was not quiet sure if it is the case that the synthezized logic is the same. At least, if I look into the RTL of both designs they look different. But maybe here is a very experienced user who says: "Well, you can do it this way but I would recommend to do it in an other way because . . . " Personally I wonder why it is designed in such an asynchronous way because I would prefer the synchronous way. On the other side I'm a little fearfull to change this because if I get additional wait states and maybe my whole project gets timing issues I don't understand. . . Maik
