Asynchronous adress decoder

Hi guys,

thanks for your replies!

@Jérôme: The AHDL design used to have the behaviour with NO wait states (like the diagram below in your attachment). The "Interface to User Logic" component in my heired SOPC design confirmed this because it uses a waitstate of '0'

In the first step of my porting to VHDL I made the mistake that I put the case-statement into the clock sensitive process. Therefore I had no chance to communicate with the SOPC system without any waitstates because I first had to register the adress on the first clock cycle after the master had set the adress on the avalon bus. At that time the avalon module was already reading the data which leads to an error.

After I found that out I tried to impelement the adress decoding like in the AHDL modul which seems to be combinatorical instead of synchronous.

The result was that I made an adress sensitive process in my VHDL module which (hopefully) behaves like the AHDL model.

@thepancake: That sounds interesting. Can you please specify how you can simulate a AHDL design in modelsim? As far as I knew, modelsim is only capable of Verilog or VHDL.

@FvM: I was aware about the fact that combinatorical logic is synthesizable. But I'm not quiet sure if it is reasonable to use this in an adress decoder logic. Well in my case I don't have an other chance if I would like to port the AHDL design to VHDL because as I described above the SOPV system uses no wait states. As this is an heired project, I ask myself if this sort of design is safe or if it has some hidden traps. If I say safe I mean is it common practice to implement adress decoders in combinatorical logic or is there a recommendation to implement it in synchronous logic? If so, then I have to change the SOPC module in the way to use at least 1 wait state.

I don't understand your question about the implicite or explicite default value of the AHDL code. Could you please explain?

Thanks,

Maik