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Altera_Forum
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16 years ago

Asynchronous adress decoder

Hi, I have heired an old design which contains of a lot of AHDL moduls. I would like to rewrite these moduls into VHDL so that I can simulate them in modelsim. One thing I realized is that...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I expect that on the SOPC bus, read enable and address are set on one clock edge and the data is read back on the next. In this case, it's perfect to use asynchronous logic to decode the addresses and multiplex the read data.