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Honored Contributor
Honored ContributorAsynchronous adress decoder
Hi, I have heired an old design which contains of a lot of AHDL moduls. I would like to rewrite these moduls into VHDL so that I can simulate them in modelsim. One thing I realized is that...
Altera_ForumHonored Contributor
Honored ContributorCombinational logic, as described above, is fully synthesizable. If it's also reasonable depends on the design purpose, which is unknown so far.
Your VHDL version is not exactly matching the AHDL code, I think. The latter is not writing zero to unsunused output bits or to all output bits in an "others" case. However, when not setting q in all cases, Quartus will warn about latch inference for q, which may be either intended or not, depending on the exact functional definition. P.S.: You didn't show the full AHDL code. Has the output signal an explicite or implicite default value of zero?
