Aria V Display Port core sometimes disconnected

Hi,

Transceiver architecture design is different from one FPGA family to another. So, not recommended for you to switch to other FPGA product as well.

It's preferable to stick with AV example design to debug either on your custom board or using the AV starter kit board.

For AV starter kit board debug :

• No, we don't have good way to isolate whether it is dev kit board or Bitec daughter card issue. You can check with whoever person that passed you these board to figure out whether the board is still healthy or any special board rework is done in the past or not
• Your latest NIOS II screenshot showing somehow the initialization is not completed and seems stuck.
  • Have you tried to toggle the resetn pin control via pressing push button switch 4 ?
  • Or reprogram NIOS II elf file again to see if it helps ?
• Other thing that you can check on the dev kit is launch the clock controller GUI software that comes with dev kit installer software to verify you are outputing the correct clock frequency to AV DP example design

For your own AV custom board debug :

• This is another debug direction also since our original debug goal is to verify your board SI issue via MSA log dump
• We wanted to bring up NIOS II to dump MSA log and you have successfully done it on AV started kit board
• Can you revisit your own board to bring up NIOS II and dump MSA log with "modified AV example design that match your board connection" ? This will be more meaningful than spent time to debug AV starter kit board

Thanks.

Regards,

dlim

Hi,

Next let's discuss about your MSA log file

• May I know this MSA log file is result output from AV starter kit board or your own custom board ? I presume it's AV starter kit board result ?
• From the MSA log file, you can see that the BER rate is pretty bad for all lanes.
  • If you are using AV starter kit board then byright your board signal integrity is good. It shouldn't be that bad unless there is some issue with your board or the Bitec daughter card itself
  • Ensure the Bitec daughter card is tightly connect to the board and the AV starter kit board is set with all default switch setting
  • Else you can also try with the sof file that I attached in previous post
  • You can also change DP cable or switch to test out other GPU since you already have golden ref design and board.
  • Pls try out lower video resolution as well
  • Another option is to change DP IP bit per colour (bpc) setting to either 8 to 10 to try out
• Else if the MSA log is from your own custom board then you know that your board SI is pretty bad
  • Then you will need to review your board SI issue accordingly

Thanks.

Regards,

dlim

Hi,

It's good to know that you have AV dev kit board and Bitec DP daughter card to port over the DP example design.

Yet I noticed you are not using AV starter kit board that matched with AV example design pinout setting.

• That means you need to manually check the pin connection on your AV board and modify the example design pin setting accordingly.

From your NIOS II terminal screenshot, I can see the "Started ..." print out which means NIOS II is already running. You just need to press wither "s" button or the user_pb[0] button to dump MSA log

• If it doesn't work and nothing happen then I suspect could be due to wrong clock frequency to NIOS or user_pb[0] pin assignment is not done correctly
• In short, pls ensure all the DP connection, IO standard, clock frequency, reset control and user_pb[0] setting is being taken care of to match with your AV board design

From my side, I will check next week to see if I can find AV started kit board in office to program the example design and show you screenshot of MSA dump. (I am now working from home due to Covid 19 control restriction in my country. We required permission to go back office)

Thanks for your understanding

Regards,

dlim

Let's try your best to bring up NIOS II connection first so that we can dump MSA log

Hi,

Ya, you shouldn't change NIOS II address location in your design.

• If you modify the address in QSYS then you just need to change it back
• Else if you modify the c code design then you can run "build_sw.sh" script in example design to rebuild the NIOS II software and regenerate the new ELF file again.
• Whenever you touch on the design in software folder, remember to always rebuild software to generate updated elf file, then download and program ELF file again. Else you can also recompile while Quartus project to integrate ELF file design into sof file
• You can learn more about the example design in DP user guide chapter 4
  • https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_displayport.pdf

Aux channel is a must for DP link training and policy maker communication update.

• Anyhow, Aux channel is just running at very low speed - 1MHz or 16MHz like that. There shouldn't be signal integrity concern but I do worry whether the Aux channel board design connection is done correctly or not.
• I found out DP board design guideline doc (AN745, page 9 onwards that talks about Aux channel design). You can want to check it out as well
  • https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an_745.pdf

Thanks.

Regards,

dlim

Additional note - you may want to cross check to ensure example design QSYS NIOS II clock and reset is supplied correctly.

Thanks.

Hi,

What I meant on watch out on all the clock frequency that you supply to DP design is

• You have modified DP Sink IP data rate and pixel output mode setting, then I would expect you need to modify the clock frequency supplied to example design accordingly like (DP video clock, NativePHY frequency setting, IOPLL setting and etc accordingly) Else pls revert the setting back and keep the changes min
• DP aux channel carry important debug info so you shouldn't remove it. Since you mentioned it's working on your original DP design then you just need to modify the example design
• You can learn more about the DP example design in Intel DP user guide chapter 4
  • https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_displayport.pdf

For MSA log dump debug :

• Below AN793 (page 20) show you screen shot of MSA log dump example
• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an793.pdf
• Just wonder after you press "S" and there is no respond from NIOS II terminal ?
• Another method to trigger MSA log dump is via triggering "user_pb[0]" signal port in DP example design
• If both method also failed then you may want to double check whether your NIOS II is initiated correctly ? From AN793 screen shot, I can see some green wording in NIOS II terminal showing connection setup to NIOS II CPU
• You can also try to reprogram the NIOS II elf file again in NIOS II command shell using below command, then repeat the MSA log dump procedure
  • nios2-download dp_demo.elf
  • The elf file is located in \av_sk_4k_v15_0\software\dp_demo\

Thanks.

Regards,

dlim

Hi,

There are a lot of design changes that you made. It's hard for me to comment whether everything is done correctly or not.

• The goal is we want to stay as close as to original example design with min changes
• I noticed you changes the DP Rx link rate and pixel output mode.
  • Actually it's fine to stay with default setting due to you are using example design and you don't need to worry about the clock frequency changes. DP link training will just down train from 5.4G to 1.62G
  • But now you need to watch out on all the clock frequency that you supply to DP design.
  • Pls revert back to match original DP example design if you still encounter failure in hardware testing later

Regarding the MSA log dump

• Sorry, my bad. I miss out one step.
• In NIOSII shell terminal, type nios2-terminal to enter NIOS console first
• Then press "s" to print MSA log

Thanks.

Regards,

dlim

Hi,

Don't use quartus_sh command to execute runall.tcl script in NIOS II terminal

Use below command instead then it should works.

• source runall.tcl

Let me know if you still face issue in generating the example design then I will generate and share it with you via Intel FTP server. The example design file size is quite big (~300MB). Hence, can't be shared as file attachment in this forum community.

I won't recommend to jump into debugging board SI issue until we verify it using MSA log from DP example design.

• Anyway, feel free to learn more about transceiver toolkit info in below link
• https://www.intel.com/content/www/us/en/programmable/products/design-software/fpga-design/quartus-prime/features/swf-transceiver-toolkit.html
• You can download toolkit example design and also easily google for transceiver toolkit short youtube video to get a feel on how it works. You can only verify the data integrity using PRBS generator/checker build in FPGA transceiver channel but don't expect to see fancy eye diagram from toolkit

Thanks.

Regards,

dlim

Hi,

1. Regarding Quartus timequest report.

• You shouldn't need to run additional timing analysis. By default. once you compile your design with STA optional enable. You should be able to view the Timequest compilation summary. Do you see any red wording highlight in compilation summary indicating timing violation in your design ?

1. Your DP video bandwidth is sufficient.
2. Ya, your error signal toggling looks weird. Let's use MSA log dump from Intel FPGA DP example design to better confirm your BER number. DP IP internally has coded some BER threshold value, once error assertion hit the threshold limit then MSA lock will be de-asserted

Below is the steps to generate MSA log file

1. Locate AV DP example design in your Quartus installation folder. Example path below

• C:\intelFPGA\16.1\ip\altera\altera_dp\hw_demo\av_sk_4k

1. Execute runall.tcl script in NIOS II shell terminal to generate and compile example design
2. Modify the example design FPGA device OPN and pinout to match with your board then compile design again
3. Program the DP example design sof file to your board
4. Launch NIOS II shell terminal again, press "s" to capture MSA log file

Share with me the MSA log file for both passing board and failing board then we can further analyze your failure issue.

Thanks.

Regards,

dlim