Aria V Display Port core sometimes disconnected

Hi,

Ya, you shouldn't change NIOS II address location in your design.

• If you modify the address in QSYS then you just need to change it back
• Else if you modify the c code design then you can run "build_sw.sh" script in example design to rebuild the NIOS II software and regenerate the new ELF file again.
• Whenever you touch on the design in software folder, remember to always rebuild software to generate updated elf file, then download and program ELF file again. Else you can also recompile while Quartus project to integrate ELF file design into sof file
• You can learn more about the example design in DP user guide chapter 4
  • https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_displayport.pdf

Aux channel is a must for DP link training and policy maker communication update.

• Anyhow, Aux channel is just running at very low speed - 1MHz or 16MHz like that. There shouldn't be signal integrity concern but I do worry whether the Aux channel board design connection is done correctly or not.
• I found out DP board design guideline doc (AN745, page 9 onwards that talks about Aux channel design). You can want to check it out as well
  • https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an_745.pdf

Thanks.

Regards,

dlim