Hi,
What I meant on watch out on all the clock frequency that you supply to DP design is
- You have modified DP Sink IP data rate and pixel output mode setting, then I would expect you need to modify the clock frequency supplied to example design accordingly like (DP video clock, NativePHY frequency setting, IOPLL setting and etc accordingly) Else pls revert the setting back and keep the changes min
- DP aux channel carry important debug info so you shouldn't remove it. Since you mentioned it's working on your original DP design then you just need to modify the example design
- You can learn more about the DP example design in Intel DP user guide chapter 4
For MSA log dump debug :
- Below AN793 (page 20) show you screen shot of MSA log dump example
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an793.pdf
- Just wonder after you press "S" and there is no respond from NIOS II terminal ?
- Another method to trigger MSA log dump is via triggering "user_pb[0]" signal port in DP example design
- If both method also failed then you may want to double check whether your NIOS II is initiated correctly ? From AN793 screen shot, I can see some green wording in NIOS II terminal showing connection setup to NIOS II CPU
- You can also try to reprogram the NIOS II elf file again in NIOS II command shell using below command, then repeat the MSA log dump procedure
- nios2-download dp_demo.elf
- The elf file is located in \av_sk_4k_v15_0\software\dp_demo\
Thanks.
Regards,
dlim
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