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relsaar's avatar
relsaar
Icon for New Contributor rankNew Contributor
5 years ago

Aria V Display Port core sometimes disconnected

Hi All We have a PCB board we designed with AMD 8860 GPU that sends DP video to Aria V Display Port core (Qsys). In some of our boards we sometimes have DP connection issues. The video signal goe...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


  1. Regarding Quartus timequest report.
  • You shouldn't need to run additional timing analysis. By default. once you compile your design with STA optional enable. You should be able to view the Timequest compilation summary. Do you see any red wording highlight in compilation summary indicating timing violation in your design ?
  1. Your DP video bandwidth is sufficient.
  2. Ya, your error signal toggling looks weird. Let's use MSA log dump from Intel FPGA DP example design to better confirm your BER number. DP IP internally has coded some BER threshold value, once error assertion hit the threshold limit then MSA lock will be de-asserted


Below is the steps to generate MSA log file

  1. Locate AV DP example design in your Quartus installation folder. Example path below
  • C:\intelFPGA\16.1\ip\altera\altera_dp\hw_demo\av_sk_4k
  1. Execute runall.tcl script in NIOS II shell terminal to generate and compile example design
  2. Modify the example design FPGA device OPN and pinout to match with your board then compile design again
  3. Program the DP example design sof file to your board
  4. Launch NIOS II shell terminal again, press "s" to capture MSA log file


Share with me the MSA log file for both passing board and failing board then we can further analyze your failure issue.


Thanks.


Regards,

dlim


relsaar's avatar
relsaar
Icon for New Contributor rankNew Contributor
5 years ago

Hi

I opened the NIOS II shell terminal and navegated example design location then I executed the tcl:

Ariel@Ariel /cygdrive/d/altera/15.0/ip/altera/altera_dp/hw_demo/av_sk_4k
$ quartus_sh -t runall.tcl

then I got:

Info: *******************************************************************
Info: Running Quartus II 64-Bit Shell
Info: Version 15.0.0 Build 145 04/22/2015 SJ Full Version
Info: Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
Info: Your use of Altera Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Altera Program License
Info: Subscription Agreement, the Altera Quartus II License Agreement,
Info: the Altera MegaCore Function License Agreement, or other
Info: applicable license agreement, including, without limitation,
Info: that your use is for the sole purpose of programming logic
Info: devices manufactured by Altera and sold by Altera or its
Info: authorized distributors. Please refer to the applicable
Info: agreement for further details.
Info: Processing started: Tue Jan 05 13:02:26 2021
Info: Command: quartus_sh -t runall.tcl
------------------------------------------------
can't read "QUARTUS_ROOTDIR": no such variable
while executing
"export PATH=`cygpath -u $QUARTUS_ROOTDIR/bin64`:$PATH"
(file "runall.tcl" line 24)
------------------------------------------------
Error (23031): Evaluation of Tcl script runall.tcl unsuccessful
Error: Quartus II 64-Bit Shell was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 4361 megabytes
Error: Processing ended: Tue Jan 05 13:02:28 2021
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:01

I added my path : %QUARTUS_ROOTDIR%\bin64 but was not helpful. Also tried to open an empty project add the content of av_sk_4k and run it from tools -> Tcl scripts , but it failed as well.

any idea how to proceed?

Please advise if I can run system console Transceiver toolkit to sample the display port "eye" and derive the signal quality from it? it it' s applicable please refers me suitable user guide or send instructions.

Thanks

Ariel