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relsaar's avatar
relsaar
Icon for New Contributor rankNew Contributor
5 years ago

Aria V Display Port core sometimes disconnected

Hi All We have a PCB board we designed with AMD 8860 GPU that sends DP video to Aria V Display Port core (Qsys). In some of our boards we sometimes have DP connection issues. The video signal goe...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


It's good to know that you have AV dev kit board and Bitec DP daughter card to port over the DP example design.


Yet I noticed you are not using AV starter kit board that matched with AV example design pinout setting.


  • That means you need to manually check the pin connection on your AV board and modify the example design pin setting accordingly.


From your NIOS II terminal screenshot, I can see the "Started ..." print out which means NIOS II is already running. You just need to press wither "s" button or the user_pb[0] button to dump MSA log

  • If it doesn't work and nothing happen then I suspect could be due to wrong clock frequency to NIOS or user_pb[0] pin assignment is not done correctly
  • In short, pls ensure all the DP connection, IO standard, clock frequency, reset control and user_pb[0] setting is being taken care of to match with your AV board design


From my side, I will check next week to see if I can find AV started kit board in office to program the example design and show you screenshot of MSA dump. (I am now working from home due to Covid 19 control restriction in my country. We required permission to go back office)


Thanks for your understanding


Regards,

dlim



  • relsaar's avatar
    relsaar
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi,

    I'm sorry - the setup photo I sent was taking from DisplayPort_RX_and_TX_Desgin_Example_AN_r1.pdf page 41#, my board is the Arria V starter KIT (see photo). I checked the pinout of a few signal in the project pin planner vs the schematics of my board and verify it matches. Then I recompile av_sk_4k project an this time I managed to get the log output (see MSA_LOG.txt) but there is no image on the TX and RX is not detected on my PC as a secondary screen.

    looking on the Bitec Display Port Daughter Card schematics and A5GX_STARTER_C.pdf schematics – it looks like the HSMA_TX_P4 to HSMA_TX_P0 was cross routed (e.g 4# goes to 0#) I changed that but got the same results.

    then I checked the PLL of my design example vs the above PDF and see some gaps.
    according to the pdf the top module is not top.v but sv_dp_demo.v and it looks very different from the top level entity I found at altera\15.0\ip\altera\altera_dp\hw_demo\av_sk_4k. (see image SV_DP_DEMO-Top module.jpg can be found at the pdf on page 3#)

    from the above PDF link - it looks like this Bitec Display Port Daughter Card was tested with a different example design.
    Also I discovered that our design was based on this sv_dp_demo.v entity and not the top.v.

    I managed to find this sv_dp_demo.v design example and tried to test it on the same setup but unfortunately the elf was failed to load.
    I tried to migrate this project to Quartos 15.0 but the IP upgrade was failed (see attached log)

    Please advise how can I proceed.

    Thanks

    Ariel