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Honored ContributorAnyone with Experience compiling Stratix IV device w/ over 95% utilization.
Having trouble getting timing closure with device which is over 95% full (530 GX). The design is also fast and consumes all the memory (figured i should get my money's worth). Of course 5% remaining logic is larger than some of the largest devices 5 years ago. Has anyone else had a large device that is this full?
We are currently focused on Incremental Compile which we have been fighting with 4 years (since 6.0). It looks like it may be actually working in 10.0sp1. Prior to this it was unusable and my team was stuck doing flat compiles.20 Replies
Altera_ForumMy only suggestion (but I think is the way you moved untill now) is to set partition all partition to empty except the one with problem. That speed up a lot the compiling time.
At this point set all optimization you can for speed (at least register retiming) and try to solve all. I mean you must understand all the problem you have. Maybe something is setting wrong and could be false path or multicycle. Moreover constraint all also all the "pin/ports" that are slow, else quartus try to make the bast as it can on all nets without assignment. When you've closed your time in this partition, preserve it with post fit netlist and go ahead with next partition in the same way. "Have fun"- Altera_Forum--- Quote Start --- yes and they move around based on seed. --- Quote End --- Hi, sounds really difficult. Do have still partitions in your design ? 95% uitilization means logic cells, memory ... ??? Can you post your design summary here ? Kind regards GPK
- Altera_Forum
yes and they move around based on seed.
- Altera_Forum--- Quote Start --- We have a few thousand nets still open. We see a big difference with seeds. We havent tried import/export since 8.0. Problem back then was that the tool could not deal with all the clocks. Multiple partitions were trying to use same resources. --- Quote End --- Hi, are the failing paths spread over the dessign ? Kind regards GPK
- Altera_Forum
We have a few thousand nets still open. We see a big difference with seeds.
We havent tried import/export since 8.0. Problem back then was that the tool could not deal with all the clocks. Multiple partitions were trying to use same resources. - Altera_Forum--- Quote Start --- Partitions has never worked in the past (always something that keeps full flow from working). In 10.0sp1, it seems to be working. Past problems have been with GXBs and memory IO. Probably 2k timing violations. Severity is very seed dependant. --- Quote End --- Hi, working with partitons have also drawbacks. Due to preserving the interfaces of the partition the design could not full optimized anymore. Have a look to the interfaces of your partitions. Are there ports with are not driven or tied to a fix value ? Are the timing violations between partitions or inside a partition ? If they are between partitions did you follow the recommendation to put registers to the inputs and outputs ? If your timing violations are inside a partition I would setup a separate project for this part of the design. It is thrn easier for Quartus to find the best placement and routing for the timing critical part of your design. After you achieved timing closure import the result to your main project. If the timing problems are located in a block inside the partition, define a partition for the block and follow the way mentioned above. Have also a critical look to the design itself, sometimes it is much easier to spend some additional registers to relax the timing. BTW: How far away are you from timing closure ? Kind regards GPK
- Altera_Forum--- Quote Start --- Hi, how many failing paths do you have ? All located in one module or spread over the design ? Do you use design partitions ? Kind regards GPK --- Quote End --- Partitions has never worked in the past (always something that keeps full flow from working). In 10.0sp1, it seems to be working. Past problems have been with GXBs and memory IO. Probably 2k timing violations. Severity is very seed dependant.
- Altera_Forum
We have been doing seed sweeps. We are now investigating (doing) DSE on individual Partitions. As you can imagine, this is a very long process with unkown results. We are locking stuff down as we get closure (over 60% now locked down). I expect what we are going to find out is the design no longer fits (It will greater than 100% total).
Thanks! - Altera_Forum
Have you tried seed sweeps? On any design I have that is on the edge of being full or on timing, I have to perform seed sweeps with the DSE in order to get a compile that both fits and meets timing. Yes it takes time, but it does work if you design is actually capable of working. Give it a try, although I'm sure your compile times are already long with that part and size, so probably not what you wanted to hear.
- Altera_Forum--- Quote Start --- Having trouble getting timing closure with device which is over 95% full (530 GX). The design is also fast and consumes all the memory (figured i should get my money's worth). Of course 5% remaining logic is larger than some of the largest devices 5 years ago. Has anyone else had a large device that is this full? We are currently focused on Incremental Compile which we have been fighting with 4 years (since 6.0). It looks like it may be actually working in 10.0sp1. Prior to this it was unusable and my team was stuck doing flat compiles. --- Quote End --- Hi, how many failing paths do you have ? All located in one module or spread over the design ? Do you use design partitions ? Kind regards GPK
