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Altera_Forum's avatar
Altera_Forum
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15 years ago

Anyone with Experience compiling Stratix IV device w/ over 95% utilization.

Having trouble getting timing closure with device which is over 95% full (530 GX). The design is also fast and consumes all the memory (figured i should get my money's worth). Of course 5% remainin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

My only suggestion (but I think is the way you moved untill now) is to set partition all partition to empty except the one with problem. That speed up a lot the compiling time.

At this point set all optimization you can for speed (at least register retiming) and try to solve all. I mean you must understand all the problem you have.

Maybe something is setting wrong and could be false path or multicycle.

Moreover constraint all also all the "pin/ports" that are slow, else quartus try to make the bast as it can on all nets without assignment.

When you've closed your time in this partition, preserve it with post fit netlist and go ahead with next partition in the same way.

"Have fun"