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Altera_Forum's avatar
Altera_Forum
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15 years ago

Anyone with Experience compiling Stratix IV device w/ over 95% utilization.

Having trouble getting timing closure with device which is over 95% full (530 GX). The design is also fast and consumes all the memory (figured i should get my money's worth). Of course 5% remainin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

We have been doing seed sweeps. We are now investigating (doing) DSE on individual Partitions. As you can imagine, this is a very long process with unkown results. We are locking stuff down as we get closure (over 60% now locked down). I expect what we are going to find out is the design no longer fits (It will greater than 100% total).

Thanks!