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Altera_Forum
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15 years ago

Anyone with Experience compiling Stratix IV device w/ over 95% utilization.

Having trouble getting timing closure with device which is over 95% full (530 GX). The design is also fast and consumes all the memory (figured i should get my money's worth). Of course 5% remainin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Have you tried seed sweeps? On any design I have that is on the edge of being full or on timing, I have to perform seed sweeps with the DSE in order to get a compile that both fits and meets timing. Yes it takes time, but it does work if you design is actually capable of working. Give it a try, although I'm sure your compile times are already long with that part and size, so probably not what you wanted to hear.