Anyone with Experience compiling Stratix IV device w/ over 95% utilization.

--- Quote Start ---

Partitions has never worked in the past (always something that keeps full flow from working). In 10.0sp1, it seems to be working. Past problems have been with GXBs and memory IO.

Probably 2k timing violations. Severity is very seed dependant.

--- Quote End ---

Hi,

working with partitons have also drawbacks. Due to preserving the interfaces of the partition the design could not full optimized anymore. Have a look to the interfaces of

your partitions. Are there ports with are not driven or tied to a fix value ?

Are the timing violations between partitions or inside a partition ? If they are between

partitions did you follow the recommendation to put registers to the inputs and outputs ?

If your timing violations are inside a partition I would setup a separate project for this part of the design. It is thrn easier for Quartus to find the best placement and routing for the timing critical part of your design. After you achieved timing closure import the result to

your main project. If the timing problems are located in a block inside the partition, define

a partition for the block and follow the way mentioned above. Have also a critical look to the design itself, sometimes it is much easier to spend some additional registers to relax

the timing.

BTW: How far away are you from timing closure ?

Kind regards

GPK