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Altera_Forum
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15 years ago

Anyone with Experience compiling Stratix IV device w/ over 95% utilization.

Having trouble getting timing closure with device which is over 95% full (530 GX). The design is also fast and consumes all the memory (figured i should get my money's worth). Of course 5% remainin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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We have a few thousand nets still open. We see a big difference with seeds.

We havent tried import/export since 8.0. Problem back then was that the tool could not deal with all the clocks. Multiple partitions were trying to use same resources.

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Hi,

are the failing paths spread over the dessign ?

Kind regards

GPK